A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, and the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a first driving control line. In a page read operation, page data in a group of memory cells selected by the word line is read to sense amplifier circuits, and in at least one operation among the page write operation, the page erase operation, and the page read operation, a voltage applied to at least one of the source line, the bit line, the word line, or the first driving control line is controlled by a reference voltage generating circuit combined with a temperature-compensating circuit.

A semiconductor device including: a first silicon layer including a first single crystal silicon and a plurality of first transistors; a first metal layer disposed over the first silicon layer; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer, a connection path from the fifth metal layer to the second metal layer, where the connection path includes a via disposed through the second level, where the via has a diameter of less than 450 nm, where the fifth metal layer includes a global power distribution grid, and where a typical thickness of the fifth metal layer is greater than a typical thickness of the second metal layer by at least 50%.

A 3D semiconductor device including: a first level including a plurality of first single-crystal transistors; a plurality of memory control circuits formed from at least a portion of the plurality of first single-crystal transistors; a first metal layer disposed atop the plurality of first single-crystal transistors; a second metal layer disposed atop the first metal layer; a second level disposed atop the second metal layer, the second level including a plurality of second transistors; a third level including a plurality of third transistors, where the third level is disposed above the second level; a third metal layer disposed above the third level; and a fourth metal layer disposed above the third metal layer, where the plurality of second transistors are aligned to the plurality of first single crystal transistors with less than 140 nm alignment error, the second level includes first memory cells, the third level includes second memory cells.

A method for producing a 3D semiconductor device including: providing a first level, the first level including a first single crystal layer; forming first alignment marks and control circuits in and/or on the first level, where the control circuits include first single crystal transistors and at least two interconnection metal layers; forming at least one second level disposed above the control circuits; performing a first etch step into the second level; forming at least one third level disposed on top of the second level; performing additional processing steps to form first memory cells within the second level and second memory cells within the third level, where each of the first memory cells include at least one second transistor, where each of the second memory cells include at least one third transistor, performing bonding of the first level to the second level, where the bonding includes oxide to oxide bonding.

In a memory device, pages are arrayed in a column direction, each page constituted by memory cells arrayed in row direction on an insulating substrate. Each memory cell includes a zonal P layer. N.sup.+ layers continuous with a source line and a bit line respectively are on both sides of the P layer. Gate insulating layers surround part of the P layer continuous with the N.sup.+ layer and part of the P layer continuous with the N.sup.+ layer 3b, respectively. One side surface and the other side surface of the gate insulating layer are covered with a gate conductor layer continuous with a first plate line and a gate conductor layer continuous with a second plate line, respectively. A gate conductor layer continuous with a word line surrounds the gate insulating layer.

A memory device includes pages, each being composed of a plurality of memory cells arrayed on a substrate in row form. The memory device controls voltages to be applied to a first gate conductor layer, a second gate conductor layer, a first impurity region, and a second impurity region of each of the memory cells included in the pages to perform a page write operation of holding a hole group formed by an impact ionization phenomenon or a gate induced drain leakage current in a channel semiconductor layer, and controls voltages to be applied to the first gate conductor layer, the second gate conductor layer, the third gate conductor layer, the fourth gate conductor layer, the first impurity region, and the second impurity region to perform a page erase operation of removing the hole group out of the channel semiconductor layer. The first impurity layer of each of the memory cells is connected to a source line, the second impurity region is connected to a bit line, one of the first gate conductor layer and the second gate conductor layer is connected to a word line, and the other is connected to a first driving control line. The bit line is connected to a sense amplifier circuit via a switching circuit. When in a page read operation, the memory device reads page data in a memory cell group selected by the word line to the bit line, and performs charge sharing between the bit line and a charge sharing node of the switching circuit opposite to the bit line to accelerate a read determination by the sense amplifier circuit.

Provided on a substrate are an N.sup.+ layer connecting to a source line SL and an N.sup.+ layer connecting to a bit line BL that are located at opposite ends of a Si pillar standing in an upright position along the vertical direction, an N layer continuous with the N.sup.+ layer, an N layer continuous with the N.sup.+ layer, a first gate insulating layer surrounding the Si pillar, a first gate conductor layer surrounding the first gate insulating layer and connecting to a plate line PL, and a second gate conductor layer surrounding a second gate insulating layer surrounding the Si pillar and connecting to a word line WL. A voltage applied to each of the source line SL, the plate line PL, the word line WL, and the bit line BL is controlled to perform a data retention operation for retaining holes, which have been generated through an impact ionization phenomenon or using a gate induced drain leakage current, in a channel region of the Si pillar, and a data erase operation for removing the holes from the channel region.

There are provided the steps of forming an N.sup.+ layer 21a and a Si pillar 26 on a substrate 20, the N.sup.+ layer 21a being connected to a source line SL, the Si pillar 26 standing in a vertical direction and being composed of a P.sup.+ layer 22a in a center portion thereof and a P layer 25a surrounding the P.sup.+ layer 22a; forming an N.sup.+ layer 3b and HfO.sub.2 layers 28a and 28b of gate insulating layers on the P.sup.+ layer 22a, the N.sup.+ layer 3b being connected to a bit line BL, the HfO.sub.2 layers 28a and 28b surrounding the Si pillar 26; and forming a TiN layer 30a of a gate conductor layer and a TiN layer 30b of a gate conductor layer, the TiN layer 30a surrounding the HfO.sub.2 layer 28a and being connected to a plate line PL, the TiN layer 30b surrounding the HfO.sub.2 layer 28b and being connected to a word line WL. Voltages to be applied to the source line SL, the plate line PL, the word line WL, and the bit line BL are controlled to perform a data write operation for holding a hole group generated by an impact ionization phenomenon or a gate induced drain leakage current in the Si pillar 26 and a data erase operation for discharging the hole group from within the Si pillar 26.

An N.sup.+ layer 21 connected to a source line SL on a substrate 20 has thereon first Si pillars 22aa to 22da. The Si pillars 22aa to 22da are surrounded, and Lg1 between opposing intersections among intersections between a line X-X′ and outer peripheral edges of HfO.sub.2 layers 24a serving as gate insulating layers surrounding the Si pillars 22aa and 22ba is larger than a thickness Lg2 of the HfO.sub.2 layers 24a crossing a line Y-Y′ and is smaller than twice the thickness Lg2. Further, TiN layers 25aa and 25ba are connected to plate lines PL1a and PL1br, and TiN layers 25ab and 25bb are connected to plate lines PL2a and PL2b, the TiN layers 25aa and 25ba and the TiN layers 25ab and 25bb surrounding the HfO.sub.2 layers 24a, extending in the line X-X′ direction, and being separated from each other. Further, TiN layers 27a and 27b surround Si pillars 22ab to 22db respectively positioned on the Si pillars 22aa to 22da and are connected to word lines WL1 and WL2, and metal wiring layers 32a and 32b are connected to N.sup.+ layers 28a to 28d positioned on the Si pillars 22ab to 22db and are connected to bit lines BL1 and BL2. As a result, a dynamic flash memory cell is formed.

A memory device includes pages arranged in columns and each constituted by a plurality of memory cells on a substrate, voltages applied to a first gate conductor layer, a second gate conductor layer, a first impurity layer, and a second impurity layer in each memory cell included in each of the pages are controlled to perform a page write operation of retaining, inside a channel semiconductor layer, a group of positive holes generated by an impact ionization phenomenon or by a gate-induced drain leakage current, and the voltages applied to the first gate conductor layer, the second gate conductor layer, the first impurity layer, and the second impurity layer are controlled to perform a page erase operation of discharging the group of positive holes from inside the channel semiconductor layer. The first impurity layer of the memory cell is connected to a source line, the second impurity layer thereof is connected to a bit line, one of the first gate conductor layer or the second gate conductor layer thereof is connected to a word line, the other of the first gate conductor layer or the second gate conductor layer thereof is connected to a driving control line, and the bit lines are connected to sense amplifier circuits with a switch circuit therebetween. In a page read operation, page data in a group of memory cells selected by the word line is read to the sense amplifier circuits, and in a page sum-of-products read operation, a voltage is applied to the driving control line such that memory cell currents, in the group of memory cells, flowing into the bit lines multiply N-fold (N is a positive integer).