On a substrate, dynamic flash memory cell transistors and, on their outside, driving-signal processing circuit transistors are disposed. A source line wiring layer, a bit line wiring layer, a plate line wiring layer, and a word line wiring layer extend in the horizontal direction relative to the substrate and connect, from the outside of a dynamic flash memory region, in the perpendicular direction, to lead-out wiring layers on an insulating layer. The transistors in driving-signal processing circuit regions connect, via multilayered wiring layers, to upper wiring layers on the insulating layer. A high-thermal-conductivity layer is disposed over the entirety of the dynamic flash memory region and in a portion above the bit line wiring layer.

A semiconductor device including a substrate having a cell array area, a peripheral circuit area, and a boundary area therebetween, gate electrodes in the cell array area and in a plurality of word line trenches extending to an inside of the substrate, a device isolation layer in the peripheral circuit area of the substrate and defining active areas, and a boundary structure in the boundary area and in a boundary trench extending to the inside of the substrate may be provided. The boundary structure may include a buried insulating layer on an inner wall of the boundary trench, an insulating liner on the buried insulating layer, and a gap-fill insulating layer filling an inside of the boundary trench on the insulating liner, and an upper surface of the insulating liner may be at a lower level than an upper surface of a corresponding one of the active area.

A semiconductor device includes: a plurality of metal interconnections spaced apart over a substrate including a lower structure; a first hydrogen-containing layer covering the plurality of the metal interconnections; a dielectric layer formed over the first hydrogen-containing layer; an air gap formed between neighboring metal interconnections inside the dielectric layer; and a second hydrogen-containing layer formed over the dielectric layer.

Apparatuses and methods for controlling hydrogen diffusion to a substrate in manufacturing memory devices are described. An example apparatus includes: a substrate; an active region in the substrate; at least one first conductive material above the active region; a hydrogen source layer on the at least one first conductive material, the hydrogen source layer including hydrogen atoms and/or molecules and the hydrogen source layer configured to release the hydrogen atoms and/or molecules; a hydrogen diffusion barrier layer on the conductive layer; and at least one second conductive material above the hydrogen diffusion barrier layer, the at least one second conductive material coupled to the at least one first conductive material. The at least one first conductive material has hydrogen diffusion properties. The hydrogen diffusion barrier layer has hydrogen barrier properties.

A semiconductor device may include a substrate including a cell region and a peripheral region, bit lines on the cell region and extending in a first direction parallel to a top surface of the substrate, a lower capping pattern on a top surface of each of the bit lines, a bit line spacer on a side surface of each of the bit lines and extending to a side surface of the lower capping pattern, and a respective upper capping pattern on a top surface of the lower capping pattern. The respective upper capping pattern is on at least a portion of a top surface of the bit line spacer.

Inventive concepts relate to a semiconductor memory device. The semiconductor memory device comprising, a substrate comprising an NMOS region and a PMOS region, a first gate pattern the NMOS region of the substrate, and a second gate pattern disposed on the PMOS region of the substrate. The first gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate, the second gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate, the diffusion mitigation pattern is in contact with the first high-k layer, a stacked structure of the first gate electrode is the same as that of the second gate electrode, and the second gate pattern does not comprise the N-type work function pattern.

There is provided a semiconductor memory device capable of improving the performance and/or the reliability of a device. The semiconductor memory device includes a substrate having a cell area and a peripheral area defined along a periphery of the cell area, wherein the cell area includes an active area defined by a cell element separation film, a cell area separation film in the substrate and defining the cell area, and a plurality of storage contacts connected to the active area, and arranged along a first direction. The plurality of storage contacts includes a first storage contact, a second storage contact, and a third storage contact, wherein the second storage contact is between the first storage contact and the third storage contact, each of the first storage contact and the third storage contact contains or surrounds or defines an airgap, and the second storage contact is free of an airgap.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

A sub word-line driver circuit of a semiconductor memory device includes a first active pattern and a second active pattern in a substrate, and a gate pattern. The first active pattern includes a first drain region and a first source region of a first keeping transistor that precharges a first word-line which is inactive and extends in a first direction with a negative voltage. The second active pattern includes a second drain region and a second source region of a second keeping transistor that precharges a second word-line which is inactive and extends in the first direction with the negative voltage. The gate pattern is on a portion of the first active pattern and on a portion of the second active pattern, partially overlaps the first active pattern and the second active pattern.

Semiconductor memory devices and methods of forming the same are provided. The semiconductor devices may include a vertical insulating structure extending in a first direction on a substrate, a semiconductor pattern extending along a sidewall of the vertical insulating structure, a bitline on a first side of the semiconductor pattern, an information storage element on a second side of the semiconductor pattern and including first and second electrodes, and a gate electrode on the semiconductor pattern and extending in a second direction that is different from the first direction. The bitline may extend in the first direction and may be electrically connected to the semiconductor pattern. The first electrode may have a cylindrical shape that extends in the first direction, and the second electrode may extend along a sidewall of the first electrode.