A semiconductor structure and a memory are provided The semiconductor structure includes: a first active area pattern; a first gate pattern, a second gate pattern, a third gate pattern and a fourth gate pattern which are arranged at intervals in a first direction; a first connection pattern, arranged to connect the second gate pattern and the third gate pattern in parallel; a second connection pattern, arranged to connect the first gate pattern and the fourth gate pattern in parallel; at least two first contact hole patterns arranged in parallel; and at least two second contact hole patterns and at least two third contact hole patterns arranged in parallel.

Embodiments relate to a semiconductor structure and a fabrication method thereof. The semiconductor structure has an array region and a peripheral region, and includes: a semiconductor substrate; a memory array structure positioned above the semiconductor substrate in the array region; a peripheral circuit structure positioned above the semiconductor substrate in the peripheral region; and a conductive connection structure positioned in the semiconductor substrate to electrically connect the memory array structure and the peripheral circuit structure. The semiconductor structure and the fabrication method thereof can effectively improve performance of a memory device.

A semiconductor structure and a memory are provided. The semiconductor structure includes an active region pattern, a first type of grid patterns overlapping with the active region pattern and extending along the first direction, and a metal layer pattern extending along the first direction. The metal layer pattern is in contact with an active region pattern arranged on both sides of the first type of grid patterns through a contact hole pattern.

A semiconductor structure and a memory are provided. The semiconductor structure includes a first active area; a first gate located on the first active area, the first active area and the first gate being configured to form a first transistor; a second active area, the second active area and the first active area being arranged along a first direction, the second active area and the first active area being independent from each other; a second gate located on the second active area, and the second active area and the second gate being configured to form a second transistor, wherein sizes of the first transistor and the second transistor are same, a deviation between an electrical parameter of the first transistor and an electrical parameter of the second transistor is below a preset threshold, and the first transistor and the second transistor belong to a cross coupling amplifying unit.

A semiconductor structure formed by the method for forming the semiconductor structure includes: a substrate, on which an insulating layer is formed; metal conductive layers located on the insulating layer; and an isolation structure located between two adjacent ones of the metal conductive layers.

A semiconductor device and a related fabrication method are provided. The semiconductor device includes a conductive line on a substrate, a capping pattern that extends along an upper surface of the conductive line, a spacer structure that extends along a side surface of the conductive line and a side surface of the capping pattern, a buried contact electrically connected to the substrate, on a side surface of the spacer structure, a barrier conductive film extending along the buried contact and the spacer structure, and a landing pad electrically connected to the buried contact, on the barrier conductive film and the capping pattern, wherein an upper part of the spacer structure includes a spacer recess that is lower than or equal to an uppermost surface of the capping pattern, and the barrier conductive film extends along the spacer recess and does not cover the uppermost surface of the capping pattern.

A method for manufacturing a semiconductor device includes providing a semiconductor substrate including a first and second regions; forming a first dielectric layer on the semiconductor substrate; forming a temporary layer on the first dielectric layer; performing a first heat treatment process on the first dielectric layer and the temporary layer; removing the temporary layer to expose the first dielectric layer; and performing a second heat treatment process on the first dielectric layer.

A semiconductor device includes a substrate including cell and core regions respectively having first and second active patterns having respective, opposing sidewall surfaces at least partially defining a trench therebetween, and a boundary region between the cell and core regions, a device isolation layer on the boundary region to fill the trench, a line structure on the first active pattern and extended from the cell region to the boundary region, and a capping pattern covering an end of the line structure on the boundary region. The device isolation layer includes one or more inner surfaces at least partially defining a recess region, which is adjacent to the end of the line structure, and the capping pattern is extended along the end of the line structure into the recess region. A top surface of the device isolation layer is between the line structure and a bottom surface of the capping pattern.

A memory device that operates at high speed is provided. The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

A memory device includes a substrate, an active layer that is spaced apart from the substrate and laterally oriented, a word line that is laterally oriented in parallel to the active layer along one side of the active layer, an active body that is vertically oriented by penetrating through the active layer, a bit line that is vertically oriented by penetrating through the active layer to be spaced apart from one side of the active body, and a capacitor that is vertically oriented by penetrating through the active layer to be spaced apart from another side of the active body.