Methods, systems, and devices for single-crystal transistors for memory devices are described. In some examples, a cavity may be formed through at least a portion of one or more dielectric materials, which may be deposited above a deck of memory cells. The cavity may include a taper, such as a taper toward a point, or a taper having an included angle that is within a range, or a taper from a cross-sectional area to some fraction of the cross-sectional area, among other examples. A semiconductor material may be deposited in the cavity and above the one or more dielectric materials, and formed in a single crystalline arrangement based on heating and cooling the deposited semiconductor material. One or more portions of a transistor, such as a channel portion of a transistor, may be formed at least in part by doping the single crystalline arrangement of the semiconductor material.

A semiconductor device may include a substrate, a patterned structure, a filling pattern, and a conductive spacer. The substrate may include a semiconductor chip region and an overlay region. The patterned structure may include bit line structures spaced by a first distance on the semiconductor region, define a first trench and a second trench on first and second regions of the overlay region, and include key structures on the second region and spaced apart by the second trench. The filling pattern may fill lower portions of the first and second trenches on the first and second regions. The first region may be an edge portion of the overlay region. The second region may be a central portion of the overlay region. The conductive spacer may contact an upper surface of the filling pattern and may be on an upper sidewall of each of the first and second trenches.

Apparatuses and methods for controlling hydrogen supply in manufacturing memory devices are described. An example apparatus includes: a first capacitor disposed above a substrate; a hydrogen supply film above the first capacitor; a second capacitor above the hydrogen supply film; and a barrier film between the hydrogen supply film and the second capacitor. The hydrogen supply film provides hydrogen and/or hydrogen ions. The barrier film is hydrogen-impermeable.

An integrated circuit device includes: a plurality of bit lines extending on a substrate in a first direction parallel to an upper surface of the substrate; a plurality of insulation capping structures respectively arranged on the plurality of bit lines, extending in the first direction, and including a first insulating material; a conductive plug between two adjacent bit lines among the plurality of bit lines on the substrate; a top capping layer arranged on the plurality of insulation capping structures and including a second insulating material different from the first insulating material; and a landing pad arranged on the conductive plug and arranged on a sidewall of a corresponding insulation capping structure among the plurality of insulation capping structures and the top capping layer.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.

Described herein are three-dimensional memory arrays that include multiple layers of memory cells. The layers are stacked and bonded to each other at bonding interfaces. The layers are formed on a support structure, such as a semiconductor wafer, that is grinded down before the layers are bonded. Vias extend through multiple layers of memory cells, including through the support structures and bonding interfaces. Thinning the support structure enables a tighter via pitch, which reduces the portion of the footprint used for vias. The memory cells may include three-dimensional transistors with a recessed gate and extended channel length.

Embodiments of the present disclosure provide power to backend memory of an IC device from the back side of the device. An example IC device with back-side power delivery for backend memory includes a frontend layer with a plurality of frontend components such as frontend transistors, a backend layer (that may include a plurality of layers) with backend memory (e.g., with one or more eDRAM arrays), and a back-side power delivery structure with a plurality of back-side interconnects electrically coupled to the backend memory, where the frontend layer is between the back-side power delivery structure and the backend layer.

Disclosed herein is an apparatus that includes a driver circuit including a plurality of first transistors arranged in a first direction; a control circuit including a plurality of second transistors arranged in parallel to the plurality of first transistors, each of the plurality of second transistors being coupled to control an associated one of the first transistors; and a power gating circuit arranged between the driver circuit and the control circuit, the power gating circuit being configured to supply a first power potential to each of the plurality of first transistors.

A contact forming method may include providing a semiconductor substrate including a silicon oxide film to an interior of a chamber, subjecting a surface of the silicon oxide film to plasma nitrification treatment, supplying a source gas including TiCl.sub.4 and H.sub.2 onto the silicon oxide film subjected to the plasma nitrification treatment, and forming a barrier layer by igniting a plasma using the source gas.