In one embodiment, a programming circuit is configured to form a programming current for a silicide fuse element by using a non-silicide programming element.

A CMOS anti-fuse cell is disclosed. In one aspect, an apparatus includes an N− well and an anti-fuse cell formed on the N− well. The anti-fuse cell includes a drain P+ diffusion deposited in the N− well, a source P+ diffusion deposited in the N− well, and an oxide layer deposited on the N− well and having an overlapping region that overlaps the drain P+ diffusion. A control gate is deposited on the oxide layer. A data bit of the anti-fuse cell is programmed when a voltage difference between the control gate and the drain P+ diffusion exceeds a voltage threshold of the oxide layer and forms a leakage path from the control gate to the drain P+ diffusion. The leakage path is confined to occur in the overlapping region.

An integral multifunction chip is provided. The integral multifunction chip includes an electronic fuse and an interface fuse. The interface fuse and the electronic fuse are disposed in parallel and integrated in a single chip. In a case where only a single chip is provided, the integral multifunction chip of the present disclosure can be selectively operated in a working mode of the electronic fuse or the interface fuse, so that convenience of use of the integral multifunction chip can be improved.

An antifuse cell includes an antifuse capacitor that is activatable with a breakdown voltage to provide an electrically conductive path through the capacitor. A pull-up transistor is coupled to the antifuse capacitor. A current path of the pull-up transistor is arranged in parallel with the antifuse capacitor. A shooting transistor is coupled to the pull-up transistor with the current paths of the pull-up transistor and a current path of the shooting transistor cascaded to each other.

A structure includes a first data line and a first anti-fuse cell including first/second programming devices and first/second reading devices. The first programming device includes a first gate and first/second source/drain regions disposing on opposite sides of first gate. The second programming device includes a second gate separate from the first gate and coupled to a first word line and third/fourth source/drain regions disposing on opposite sides of second gate. The first reading device includes a third gate and fifth/sixth source/drain regions disposing on opposite sides of third gate. The second reading device includes a fourth gate and seventh/eighth source/drain regions disposing on opposite sides of fourth gate. The third/fourth gates are parts of the first continuous gate coupled to a second word line. The fifth/seventh source/drain regions are coupled to the second/fourth source/drain regions, respectively. The sixth/eighth source/drain regions are coupled to the first data line.

The present application provides a programmable memory device. The programmable memory device includes: an access transistor, comprising an active region formed in a substrate and a gate structure formed on the substrate, wherein the active region has a linear top view shape, the gate structure has a first portion and a second portion, the first portion is intersected with a section of the active region away from end portions of the active region, and the second portion is laterally spaced apart from the active region; and a capacitor, using a portion of the active region as a terminal, and further comprising an electrode and a dielectric layer, wherein the electrode is disposed on the portion of the active region and spaced apart from the gate structure, and at least a portion of the dielectric layer is sandwiched between the electrode and the portion of the active region.

An antifuse structure includes an active area, a gate electrode and a dielectric layer. The gate electrode is over the active area, in which the gate electrode is ring-shaped, and a portion of the gate electrode is overlapped with a portion of the active area in a vertical projection direction, and the portion of the active area has a dopant concentration higher than a dopant concentration of another portion of the active area. The dielectric layer is sandwiched between the portion of the active area and the portion of the gate electrode.

A memory element according to an embodiment includes: first through fourth impurity layers arranged in a semiconductor layer including first to third portions; a first gate wiring line disposed on the first portion located between the first and second impurity layers; a second gate wiring line disposed on the second portion located between the second and third impurity layers; a third gate wiring line disposed on the third portion located between the third and fourth impurity layers; a first insulating layer disposed between the first portion and the first gate wiring line; a second insulating layer disposed between the second portion and the second gate wiring line; a third insulating layer disposed between the third portion and the third gate wiring line; first wiring line electrically connected to the first through third gate wiring lines; and second wiring line electrically connected to the first through fourth impurity layers.

An integrated circuit is disclosed. The integrated circuit includes a transistor, a first fuse element and a second fuse element. The transistor is formed in a first conductive layer. The first fuse element is formed in a second conductive layer disposed above the first conductive layer. The second fuse element is formed in the second conductive layer and is coupled to the first fuse element. The transistor is coupled through the first fuse element to a first data line for receiving a first data signal, and the transistor is coupled through the second fuse element to a second data line for receiving a second data signal. A method of fabricating an integrated circuit (IC) is also disclosed herein.

Provided is a semiconductor device including a substrate, a tunneling insulating film disposed on the substrate, a control gate electrode disposed on the tunneling insulating film, a first floating gate electrode disposed between the control gate electrode and the tunneling insulating film, a second floating gate electrode disposed between the first floating gate electrode and the tunneling insulating film, a first control gate insulating film disposed between the first floating gate electrode and the control gate electrode, a second control gate insulating film disposed between the second floating gate electrode and the first floating gate electrode, and a source electrode and a drain electrode disposed on the substrate to be spaced apart from each other with respect to the control gate electrode, wherein the control gate electrode includes a first metal material, wherein the first floating gate electrode includes a second metal material, wherein the second floating gate electrode includes a third metal material, wherein the first to third metal materials are different from each other, wherein an oxidizing power of the second metal material is smaller than an oxidizing power of the first metal material.