A semiconductor structure and a method for manufacturing the semiconductor structure are provided. The semiconductor structure includes: a substrate including a first doped region; a first isolation structure located in the first doped region, a depth of the first isolation structure being greater than that of the first doped region; a first gate structure located on the surface of the substrate of the first doped region and spanning the first isolation structure, a projection width of the first gate structure on the substrate being larger than that of the first isolation structure on the substrate; and second gate structures located on the surface of the substrate and at both sides of the first gate structure.

A one-time programmable nonvolatile memory cell includes a substrate providing a first conductivity type well and a second conductivity type well, a first MOS transistor having a floating gate and a gate oxide, and an auxiliary gate and a gate oxide formed by extending one end of the floating gate and the gate oxide of the first MOS transistor from an edge of the first active region, along a second direction perpendicular to the first direction, passing through the isolation region until to cover a part or an entire of the second active region. The first and the second active regions are separated by an isolation region, and the first and second active regions and the isolation region are arranged parallel to each other along a first direction. The memory cell has an improved structure and optimized performance and a reduced size.

A one-time programmable nonvolatile memory cell includes a substrate providing a first conductivity type well and a second conductivity type well, a first MOS transistor having a floating gate and a gate oxide, and an auxiliary gate and a gate oxide formed by extending one end of the floating gate and the gate oxide of the first MOS transistor from an edge of the first active region, along a second direction perpendicular to the first direction, passing through the isolation region until to cover a part or an entire of the second active region. The first and the second active regions are separated by an isolation region, and the first and second active regions and the isolation region are arranged parallel to each other along a first direction. The memory cell has an improved structure and optimized performance and a reduced size.

A semiconductor metal-oxide-semiconductor field effect transistor (MOSFET) with increased on-state current obtained through a parasitic bipolar junction transistor (BJT) of the MOSFET. Methods of operating the MOSFET as a memory cell or a memory array select transistor are provided.

A semiconductor circuit and semiconductor device for determining status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a latch circuit for reading a first status signal of a first node between the configurable reference resistor unit and the fuse element. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

A semiconductor circuit and semiconductor device for determining status of a fuse element are provided. The semiconductor circuit includes a configurable reference resistor unit with a first terminal receiving a first power signal and a second terminal electrically coupled to the fuse element. The semiconductor circuit also includes a latch circuit for reading a first status signal of a first node between the configurable reference resistor unit and the fuse element. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to be provided to the gate of the first transistor.

The present disclosure provides a method for determining status of a fuse element of a memory device. The method includes providing the memory device including a first terminal and a second terminal and applying a first power signal on the first terminal of the semiconductor device. The memory device includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

The present disclosure provides a method for determining status of a fuse element of a memory device. The method includes providing the memory device including a first terminal and a second terminal and applying a first power signal on the first terminal of the semiconductor device. The memory device includes a configurable reference resistor unit electrically coupled to the fuse element. The method also includes obtaining an evaluation signal at the second terminal of the memory device and identifying the evaluation signal to determine whether the memory device is redundant. The configurable reference resistor unit includes a first resistor, a first transistor connected in parallel with the first resistor, and a first configurable unit connected to a gate of the first transistor. The first configurable unit is configured to generate a first configurable signal to turn on the first transistor.

An IC device includes first through third device pairs positioned in first through third active areas extending in a first direction, each pair including first and second transistors coupled between respective first and second anti-fuse structures and a shared bit line contact, and each of the first and third active areas being adjacent to the second active area. First through fourth conductive lines extend in a second direction, first and second conductive paths couple the first conductive line to the first anti-fuse structures, a third conductive path couples the fourth conductive line to the second anti-fuse structures, and a fourth conductive path couples the third conductive line to the second transistors. The first and third conductive paths are aligned along the first direction between the first and second active areas, and the second and fourth conductive paths are aligned along the first direction between the second and third active areas.

An IC device includes first through third device pairs positioned in first through third active areas extending in a first direction, each pair including first and second transistors coupled between respective first and second anti-fuse structures and a shared bit line contact, and each of the first and third active areas being adjacent to the second active area. First through fourth conductive lines extend in a second direction, first and second conductive paths couple the first conductive line to the first anti-fuse structures, a third conductive path couples the fourth conductive line to the second anti-fuse structures, and a fourth conductive path couples the third conductive line to the second transistors. The first and third conductive paths are aligned along the first direction between the first and second active areas, and the second and fourth conductive paths are aligned along the first direction between the second and third active areas.