A memory device includes first nanostructures stacked on top of one another; first gate stacks, where two adjacent ones of the first gate stacks wrap around a corresponding first nanostructure; second nanostructures stacked on top of one another; second gate stacks, where two adjacent ones of the second gate stacks wrap around a corresponding second nanostructure; a first drain/source feature electrically coupled to a first end of the first nanostructures; a second drain/source feature electrically coupled to both of a second end of the first nanostructures and a first end of the second nanostructures; and a third drain/source feature electrically coupled to a second end of the second nanostructures. At least one of the plurality of first gate stacks is in direct contact with at least one of the first drain/source feature or the second drain/source feature.

A semiconductor device includes first nanostructures vertically separated from one another, a first gate structure wrapping around each of the first nanostructures, and second nanostructures vertically separated from one another. The semiconductor device also includes a second gate structure wrapping around the second nanostructures, a first drain/source structure coupled to a first end of the first nanostructures, a second drain/source structure coupled to both of a second end of the first nanostructures and a first end of the second nanostructures, and a third drain/source structure coupled to a second end of the second nanostructures. The first drain/source structure has a first doping type, the second and third drain/source structures have a second doping type, and the first doping type is opposite to the second doping type.

A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a plurality of second nanostructures extending along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a first sidewall of each of the plurality of first nanostructures along a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewalls. The semiconductor device includes a second gate structure straddling the plurality of second nanostructures.

The present application discloses a method for fabricating a semiconductor device includes providing a substrate, forming a gate stack on the substrate and a pair of heavily-doped regions in the substrate, forming a programmable contact having a first width on the gate stack, and forming a first contact having a second width, which is greater than the first width, on one of the pair of heavily-doped regions.

A transistor includes: a gate structure disposed on a substrate, and including a gate insulation layer and a gate electrode; a first impurity region disposed at an upper portion of a substrate and adjacent to a first sidewall of the gate structure; a second impurity region disposed at an upper portion of the substrate and adjacent to a second sidewall opposite to the first sidewall of the gate structure; and a first threshold voltage controlling line spaced apart from the substrate, wherein the first threshold voltage controlling line faces at least a portion of the first impurity region, wherein the first threshold voltage controlling line includes a conductive material, and wherein the first threshold voltage controlling line extends in a direction that crosses a direction in which the first impurity region extends.

A semiconductor integrated circuit device includes a standard cell on a substrate, an one time programmable (OTP) memory structure at an edge portion of the standard cell, and a program transistor outside of the standard cell at a position adjacent to the edge portion of the standard cell at which the OTP memory structure is provided, the program transistor being electrically connected to the OTP memory structure. The OTP memory structure includes a first anti-fuse and a second anti-fuse. When a program voltage is applied to the program transistor and a bias power voltage is applied to the OTP memory structure, each of the first anti-fuse and the second anti-fuse becomes shorted and the bias power voltage is provided to the standard cell.

A semiconductor integrated circuit device includes a standard cell on a substrate, an one time programmable (OTP) memory structure at an edge portion of the standard cell, and a program transistor outside of the standard cell at a position adjacent to the edge portion of the standard cell at which the OTP memory structure is provided, the program transistor being electrically connected to the OTP memory structure. The OTP memory structure includes a first anti-fuse and a second anti-fuse. When a program voltage is applied to the program transistor and a bias power voltage is applied to the OTP memory structure, each of the first anti-fuse and the second anti-fuse becomes shorted and the bias power voltage is provided to the standard cell.

A semiconductor device includes a plurality of first nanostructures extending along a first lateral direction. The semiconductor device includes a first epitaxial structure and second epitaxial structure respectively coupled to ends of each of the plurality of first nanostructures along the first lateral direction. The semiconductor device includes a dielectric fin structure disposed immediately next to a sidewall of each of the plurality of first nanostructures facing a second lateral direction perpendicular to the first lateral direction. The semiconductor device includes a first gate structure wrapping around each of the plurality of first nanostructures except for the sidewalls of the first nanostructures. The semiconductor device includes a metal structure disposed above the first gate structure and coupled to one of the first or second epitaxial structure.

An integrated circuit includes a TSV extending from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate and having a first end and a second end, and a non-volatile repair circuit. The non-volatile repair circuit includes a one-time programmable (OTP) element having a programming terminal, wherein in response to an application of a fuse voltage to the programming terminal, the OTP element electrically couples the first end of the TSV to the second end of the TSV.

An integrated circuit includes a TSV extending from a first surface of a semiconductor substrate to a second surface of the semiconductor substrate and having a first end and a second end, and a non-volatile repair circuit. The non-volatile repair circuit includes a one-time programmable (OTP) element having a programming terminal, wherein in response to an application of a fuse voltage to the programming terminal, the OTP element electrically couples the first end of the TSV to the second end of the TSV.