Disclosed are a semiconductor structure, a memory and a method for operating the memory. The semiconductor structure includes: a substrate; a first gate structure and a second gate structure that are located on a surface of the substrate and have a same thickness smaller than a preset thickness; and a first doped area and a second doped area that are located in the substrate and are respectively located on two sides of the first gate structure. The first gate structure forms a selection transistor with the first and second doped areas; an orthographic projection of the second gate structure on the substrate is at least partially overlapped with the second doped area. The second gate structure and the second doped area form an antifuse bit structure. A breakdown state and a non-breakdown state of the antifuse bit structure are configured to represent different stored data.

A 3D semiconductor device including: a first single crystal layer with first transistors; overlaid by a first metal layer; a second metal layer overlaying the first metal layer and being overlaid by a third metal layer; a logic gates including at least the first metal layer interconnecting the first transistors; second transistors disposed atop the third metal layer; third transistors disposed atop the second transistors; a top metal layer disposed atop the third transistors; and a memory array including word-lines, and at least four memory mini arrays, where each of the memory mini arrays includes at least four rows by four columns of memory cells, where each of the memory cells includes at least one of the second transistors or third transistors, sense amplifier circuit(s) for each of the memory mini arrays, the second metal layer provides a greater current carrying capacity than the third metal layer.

The present disclosure relates to a method to form an integrated chip including a filament via. In some embodiments, a lower metal layer comprising a first metal line and a second metal line is formed over a substrate. A filament dielectric layer is formed over the lower metal layer. An upper metal layer comprising a first metal line and a second metal line is formed over the filament dielectric layer. A first contact is formed over the upper metal layer. A filament formation bias is applied through the first contact to form a first filament via through the filament dielectric layer and electrically connecting the first metal line of the lower metal layer and the first metal line of the upper metal layer.

An integrated circuit (IC) device includes transistor and programmable structure regions. The transistor region includes a source structure configured to receive a reference voltage, a first portion of a drain structure, and a gate electrode positioned between the source structure and the first portion of the drain structure, and configured to receive an activation signal. The programmable structure region includes a second portion of the drain structure, a first signal line configured to receive an operational voltage, a second signal line, a gate via underlying and electrically connected to the first signal line, and a drain via positioned between and electrically connected to the second portion of the drain structure and the second signal line. Portions of the first signal line including a gate via location and the second signal line including a drain via location are positioned in parallel in a same metal layer of the IC device.

A semiconductor device is provided. The semiconductor device includes a metal-oxide-semiconductor field-effect-transistor (MOSFET) device electrically attachable to a first data line and a read-only memory (ROM) element. The ROM element is electrically interposable between the MOSFET device and a second data line. The ROM element includes first and second sets of memory cells in high and low resistance states, respectively, to form a secure identifier (ID).

An operation method of a multi-bits read only memory includes a step of applying a gate voltage to a conductive gate, a first voltage to a first electrode, and a second voltage to a second electrode. The multi-bits read only memory of the present invention includes a substrate and a transistor structure with the conductive gate mounted between the first electrode and the second electrode. A multiplicity of M nanowire channels is mounted between the first electrode and the second electrode, and M is a positive integer greater than one. The present invention breaks multiple states of the multi-bits read only memory. The multiple states are programmable and include an i.sup.th state, and 1 <i <M . The aforementioned states allow storage of multiple bits on the read only memory, instead of just storing a single bit on the read only memory.

A One Time Programmable (OTP) memory can have a memory cell, which includes two series diodes as a fuse structure.

A one time programmable non-volatile memory cell includes a storage element. The storage element includes a glass substrate, a buffer layer, a polysilicon layer and a metal layer. The buffer layer is disposed on the glass substrate. The polysilicon layer is disposed on the buffer layer. A P-type doped region and an N-type doped region are formed in the polysilicon layer. The metal layer is contacted with the N-type doped region and the P-type doped region. The metal layer, the N-type doped region and the P-type doped region are collaboratively formed as a diode. When a program action is performed, the first diode is reverse-biased, and the diode is switched from a first storage state to a second storage state. When a read action is performed, the diode is reverse-biased and the diode generates a read current.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

The present disclosure provides an antifuse array structure and a memory. The antifuse array structure includes a plurality of antifuse integrated structures arranged in a bit line extension direction and a word line extension direction to form an antifuse matrix. The antifuse integrated structure is arranged in a same active region, and an extension direction of the active region is the same as the bit line extension direction. Each antifuse integrated structure includes a first antifuse memory MOS transistor, a first switch transistor, a second switch transistor, and a second antifuse memory MOS transistor. The first switch transistor and the second switch transistor are respectively controlled through two adjacent word lines, the first antifuse memory MOS transistor and the second antifuse memory MOS transistor are respectively controlled through two adjacent programming wires, and the programming wire is further configured to control adjacent antifuse integrated structures.