A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

A semiconductor structure includes a first source/drain region, a second source/drain region, a channel doping region, a gate structure, a first well and a second well. The second source/drain region is disposed opposite to the first source/drain region. The channel doping region is disposed between the first source/drain region and the second source/drain region. The gate structure is disposed on the channel doping region. The first well has a first portion disposed under the first source/drain region. The second well is disposed opposite to the first well and separated from the second source/drain region. The first source/drain region, the second source/drain region and the channel doping region have a first conductive type. The first well and the second well have a second conductive type different from the first conductive type.

A semiconductor' device may include: a substrate; a first well region formed on the substrate; a second well region formed on the substrate, the first well region and the second well region extending in a first direction and being adjacent to each other in a second direction crossing the first direction; a first active region formed in the first well region; a first power region formed in the first well region, the first active region and the first power region being separate from each other in the first direction; a second active region array formed in the second well region; a second power region formed in the second well region, the second active region array and the second power region being separate from each other in the first direction; and a first dummy active region formed in the first well region between the first active region and the first power region, the first dummy active region being separate from the first active region and the first power region in the first direction.

Semiconductor chips are provided. A semiconductor chip includes a peripheral circuit region on a substrate. The semiconductor chip includes a semiconductor layer on the peripheral circuit region. The semiconductor chip includes a cell region on the semiconductor layer. Moreover, the semiconductor chip includes a layer/connector that is adjacent the semiconductor layer. Methods of manufacturing semiconductor chips are also provided.

Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.

A method of fabricating a memory device includes forming a plurality of first nanostructures, a plurality of second nanostructures, a plurality of third nanostructures, and a plurality of fourth nanostructures; separating the plurality of first nanostructures and the plurality of second nanostructures with a dielectric fin structure; forming a first gate structure wrapping around each of the first nanostructures except for a sidewall that is in contact with the dielectric fin structure; forming a second gate structure wrapping around each of the second nanostructures except for a sidewall that is in contact with the dielectric fin structure; and forming a first interconnect structure coupled to one of the first gate structure or second gate structure. The dielectric structure also extends along the first lateral direction. The first and second gate structures extend along a second lateral direction perpendicular to the first lateral direction.

Methods of forming a transistor might include removing portions of a semiconductor to define a semiconductor fin having an upper portion having an uppermost surface at a first level and extending from the first level to a second level, and a lower portion, wider than the upper portion, having an uppermost surface at the second level and extending from the second level to a third level; forming first and second isolation regions at the third level and adjacent the lower portion of the semiconductor fin; forming a first dielectric overlying portions of the semiconductor that are lower than a level between the first level and the second level; forming a second dielectric overlying an exposed portion of the upper portion of the semiconductor fin; forming a conductor overlying the second dielectric; and forming first and second source/drains in the lower portion of the semiconductor fin at the second level.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A semiconductor device includes a substrate, and interconnects provided above the substrate. The device further includes a first insulator that is provided on the interconnects and on air gaps provided between the interconnects, surrounds the interconnects from lateral sides of the interconnects, and is formed of a first insulating material. The device further includes a second insulator that surrounds an interconnect region including the interconnects and the air gaps from the lateral sides of the interconnects through the first insulator, includes no portion provided between the interconnects, and is formed of a second insulating material different from the first insulating material.

A memory device includes a substrate, and a peripheral circuit disposed on a first surface of the substrate. The peripheral circuit includes a first transistor. The memory device further includes a first wiring layer disposed on the peripheral circuit, a base layer disposed on the first wiring layer, a memory cell array disposed on the base layer, and a second wiring layer disposed on the memory cell array. The second wiring layer includes a first power wiring configured to supply a first voltage, a second power wiring configured to supply a second voltage, and a first wiring electrically connected to the first transistor. The first wiring is configured to be electrically connectable to either the first power wiring or the second power wiring.