A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

An integrated circuit includes a data processing circuit, an electrostatic discharge (ESD) protection circuit which is connected between a voltage rail and a ground rail and protects the data processing circuit from an ESD event on the voltage rail, and a switch circuit for controlling a connection between the voltage rail and the data processing circuit in response to a control signal.

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

A one time programmable (OTP) memory cell includes a select gate transistor, a following gate transistor, and an antifuse varactor. The select gate transistor has a first gate terminal, a first drain terminal and a first source terminal. The following gate transistor has a second gate terminal, a second drain terminal and a second source terminal coupled to the first drain terminal. The antifuse varactor has a third gate terminal, a third drain terminal, and a third source terminal coupled to the second drain terminal. The select gate transistor, the following gate transistor, and the antifuse varactor are formed on a substrate structure.

A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P- and NSi beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

A memory device including a substrate, a sense amplifier that includes first gate-all-around transistors that have first drain/source regions that extend into the substrate, and bit cells that include fuse memory elements and second gate-all-around transistors. Each of the bit cells includes a fuse memory element having a first terminal connected to an input of the sense amplifier and a second terminal connected to a second gate-all-around transistor that includes second drain/source regions and a bottom dielectric isolation layer under the second drain/source regions.

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.

A technology precluding attacks through peripheral devices thefts to a network of electronic appliances, by utilizing physical chip identification devices, is disclosed. The electronic appliances in the network are divided into the peripheral devices and the stem servers managing the registration information of the peripheral devices. The stem servers are under the central control with software, and the peripheral devices are controlled at device-level with the physical chip identification devices implemented in the chip. Thus, the security of the whole network is efficiently enhanced.