A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P—and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

According to one embodiment, a semiconductor device includes a transistor having a diffusion layer extending along a surface of a substrate and a gate electrode arranged above the diffusion layer; and contacts having elongated bottom surfaces connected to the diffusion layer on both sides of the gate electrode, in which the contacts are arranged so that the bottom surfaces of the contacts are not aligned in a straight line with an extension direction of the diffusion layer.

There are provided a semiconductor memory device and a manufacturing method thereof. The semiconductor memory device includes: a cell source structure; a first stack structure disposed on the cell source structure; a channel structure penetrating the first stack structure, the channel structure being connected to the cell source structure; and a first peripheral transistor including impurity regions. A level of a bottom surface of each of the impurity regions is higher than that of a bottom surface of the cell source structure, and a level of a top surface of each of the impurity regions is lower than that of a top surface of the cell source structure.

The disclosed technology relates generally to semiconductor devices and manufacturing methods thereof, and more particularly to field-effect transistors operating at different voltages and methods for integrating the same. In one aspect, a method of fabricating a semiconductor device comprises: a) providing a substrate and a first hardmask; b) next, providing a second hardmask over a first region of the first hardmask; c) next, forming a first set of hardmask fins in a second region of the first hardmask; d) next, masking the second region; e) next, providing a set of photoresist fins on the second hardmask; f) next, patterning the second hardmask and the first region by using the photoresist fins as a mask; g) next, forming a first set of semiconductor fins of a first height by etching the substrate; h) next, removing the mask provided in step d; i) next, forming a second set of semiconductor fins of a second height in the second region and extending the height of the first set of semiconductor fins to a third height in the first region, by etching the substrate by using the first and second sets of hardmask fins as masks.

A low cost IC solution is disclosed to provide Super CMOS microelectronics macros. Hereinafter, the Super CMOS or Schottky CMOS all refer to SCMOS. The SCMOS device solutions with a niche circuit element, the complementary low threshold Schottky barrier diode pairs (SBD) made by selected metal barrier contacts (Co/Ti) to P— and N—Si beds of the CMOS transistors. A DTL like new circuit topology and designed wide contents of broad product libraries, which used the integrated SBD and transistors (BJT, CMOS, and Flash versions) as basic components. The macros include diodes that are selectively attached to the diffusion bed of the transistors, configuring them to form generic logic gates, memory cores, and analog functional blocks from simple to the complicated, from discrete components to all grades of VLSI chips. Solar photon voltaic electricity conversion and bio-lab-on-a-chip are two newly extended fields of the SCMOS IC applications.

An integrated circuit device of an embodiment includes a substrate, a first transistor, an insulation layer, a first contact, a second contact, and a first single crystal portion. The first transistor includes a first gate electrode, and a first drain region, and wherein the first source region and the first drain region are disposed in the substrate. The first contact faces the first gate electrode. The second contact faces a first region that is first one of the first source region and the first drain region. The first single crystal portion is disposed on the first region and convex from a surface of the first region, and is located between the first region and the second contact.

A stack of sacrificial layers is formed in a set of N levels. A first etch-trim mask having spaced apart first and second open etch regions is formed over the set. Two levels are etched through using the first etch-trim mask in each of M etch-trim cycles, where M is (N−1)/2 when N is odd and (N/2)−1 when N is even. One level is etched through using the first etch-trim mask in one etch-trim cycle when N is even. The first etch-trim mask is trimmed to increase the size of the first and second open etch regions, in each of etch-trim cycles C(i) for i going from 1 to T−1, where T is (N−1)/2 when N is odd and N/2 when N is even. A second etch mask is formed over the set, covering one of the open etch regions. One level is etched through using the second etch mask.

A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.

An integrated circuit device includes a memory including a memory cell insulation surrounding a memory stack and a memory cell interconnection unit, a peripheral circuit including a peripheral circuit region formed on a peripheral circuit board, and a peripheral circuit interconnection between the peripheral circuit region and the memory structure, a plurality of conductive bonding structures on a boundary between the memory cell interconnection and the peripheral circuit interconnection in a first region, the first region overlapping the memory stack in a vertical direction, and a through electrode penetrating one of the memory cell insulation and the peripheral circuit board and extended to a lower conductive pattern included in the peripheral circuit interconnection in a second region, the second region overlapping the memory cell insulation in the vertical direction.