A nonvolatile memory device and a method of manufacturing the device, the device including a first semiconductor layer, the first semiconductor layer including an upper substrate, and a memory cell array, the memory cell array including a plurality of gate conductive layers stacked on the upper substrate and a plurality of pillars passing through the plurality of gate conductive layers and extending in a direction perpendicular to a top surface of the upper substrate; and a second semiconductor layer under the first semiconductor layer, the second semiconductor layer including a lower substrate, at least one contact plug between the lower substrate and the upper substrate, and a common source line driver on the lower substrate and configured to output a common source voltage for the plurality of pillars through the at least one contact plug.

A semiconductor device includes a substrate, a peripheral structure, a lower insulating layer, and a stack. The substrate includes a peripheral circuit region and a cell array region. The peripheral structure is on the peripheral circuit region. The lower insulating layer covers the peripheral circuit region and the cell array region and has a protruding portion protruding from a flat portion. The stack is on the lower insulating layer and the cell array region, and includes upper conductive patterns and insulating patterns which are alternately and repeatedly stacked.

A semiconductor structure including a semiconductor substrate and at least one patterned dielectric layer is provided. The semiconductor substrate includes a semiconductor portion, at least one first device, at least one second device and at least one first dummy ring. The at least one first device is disposed on a first region surrounded by the semiconductor portion. The at least one second device and the at least one first dummy ring are disposed on a second region, and the second region surrounds the first region. The at least one patterned dielectric layer covers the semiconductor substrate.

A stack of sacrificial layers is formed in a set of N levels. A first etch-trim mask having spaced apart first and second open etch regions is formed over the set. Two levels are etched through using the first etch-trim mask in each of M etch-trim cycles, where M is (N1)/2 when N is odd and (N/2)1 when N is even. One level is etched through using the first etch-trim mask in one etch-trim cycle when N is even. The first etch-trim mask is trimmed to increase the size of the first and second open etch regions, in each of etch-trim cycles C(i) for i going from 1 to T1, where T is (N1)/2 when N is odd and N/2 when N is even. A second etch mask is formed over the set, covering one of the open etch regions. One level is etched through using the second etch mask.

A method of using a chip identification device is jointly performed by a chip mass-produced by a semiconductor manufacturing process, a first chip manufacturer making the chip, and a chip user assembling a product by using the chip. The method includes inputting a first published passcode, published by the first chip manufacturer, inputting a second published passcode published by a second chip manufacturer, inputting the first published passcode to the chip by the chip user, reading an aggregate of electronic output signals as a read code, sending the read code to the first chip manufacturer to compare the first output code and the read code. The chip is regarded as a counterfeit if the comparison is consistent.

A semiconductor device includes a plurality of high-voltage insulated-gate field-effect transistors arranged in a matrix form on the main surface of a semiconductor substrate and each having a gate electrode, a gate electrode contact formed on the gate electrode, and a wiring layer which is formed on the gate electrode contacts adjacent in a gate-width direction to electrically connect the gate electrodes arranged in the gate-width direction. And the device includes shielding gates provided on portions of an element isolation region which lie between the transistors adjacent in the gate-width direction and gate-length direction and used to apply reference potential or potential of a polarity different from that of potential applied to the gate of the transistor to turn on the current path of the transistor to the element isolation region.

Some embodiments include apparatus and methods using a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; a first channel region located between a portion of the first diffusion region and a portion of the third diffusion region; a second channel region located between the portion of the third diffusion region and a portion of the second diffusion region; a third channel region located between the portion of the second diffusion region and a portion of the fourth diffusion region; and a gate located over the first, second, and third channel regions. The first and second diffusion regions are located on a first side of the gate. The third and fourth diffusion regions are located on a second side of the gate opposite from the first side.

Various implementations described herein relate to a device with a multi-transistor logic structure for use in memory architecture. In some applications, the multi-transistor logic structure may have a pair of P-type transistors that are arranged in a P-over-P multi-transistor stack. In other applications, the multi-transistor logic structure may have a pair of N-type transistors that are arranged in an N-over-N multi-transistor stack.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes conductive materials located in different levels of the apparatus, dielectric materials located in different levels of the apparatus, a first conductive contact, and a second conductive contact. One of the conductive materials is between two of the dielectric materials. One of the dielectric materials is between two of the conductive materials. The first conductive contact has a length extending through the conductive materials and the dielectric materials in a direction perpendicular to the levels of the apparatus. The first conductive contact is electrically separated from the conductive materials. The second conductive contact contacts a group of conductive materials of the conductive materials.

A non-volatile memory device may include a first semiconductor layer including a peripheral region, the peripheral region including one or more peripheral transistors on a lower substrate. The non-volatile memory device may further include a second semiconductor layer on the peripheral region, the second semiconductor layer including an upper substrate, the second semiconductor layer further including a memory cell array on the upper substrate. The upper substrate may include a first upper substrate on the first semiconductor layer, a first layer on the first upper substrate, and a second upper substrate on the first layer.