A method of manufacturing a memory structure including following steps is provided. Two gate stack structures are formed on a substrate. A conductive material layer is conformally formed on the two gate stack structures. The conductive material layer includes two protrusions located on the two gate stack structures. Hard mask spacers are formed on two sides of each of the two protrusions. A first etching process is performed to remove a portion of the conductive material layer by using the hard mask spacers as a mask. A second etching process is performed to completely remove the hard mask spacers. Then, a third etching process is performed on the conductive material layer to form a first conductive spacer and a second conductive spacer located on one side and the other side of the two gate stack structures and to form a conductive layer located between the two gate stack structures.

A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.

A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a plurality of barrier structures. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The plurality of barrier structures respectively wrap surfaces of the plurality of gate layers. Each barrier structure includes a first barrier layer and a second barrier layer. The first barrier layer continuously covers a top surface, a bottom surface and a first sidewall of a corresponding gate layer. The second barrier layer covers a second sidewall of the corresponding gate layer opposite to the first sidewall, and connects the first barrier layer. The second barrier layer has a thickness greater than a thickness of the first barrier layer. A method of forming a 3D memory device is also provided.

Provided is a three-dimensional (3D) memory device including: a substrate, a stack structure, and a plurality of barrier structures. The stack structure is disposed on the substrate. The stack structure includes a plurality of dielectric layers and a plurality of gate layers stacked alternately. The plurality of barrier structures respectively wrap surfaces of the plurality of gate layers. Each barrier structure includes a first barrier layer and a second barrier layer. The first barrier layer continuously covers a top surface, a bottom surface and a first sidewall of a corresponding gate layer. The second barrier layer covers a second sidewall of the corresponding gate layer opposite to the first sidewall, and connects the first barrier layer. The second barrier layer has a thickness greater than a thickness of the first barrier layer. A method of forming a 3D memory device is also provided.

A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

A method for manufacturing a cured product pattern of a curable composition includes the steps of, in sequence, depositing a droplet of the curable composition onto a substrate; bringing a mold having an uneven pattern formed in a surface thereof into contact with the curable composition; curing the curable composition; and releasing a cured product of the curable composition from the mold. The mold has a recess having a bottom surface and a stair structure arranged to form an opening surface that becomes wider from the bottom surface toward the surface of the mold. In the contact step, the curable composition comes into contact with the stair portion after a top of the droplet comes into contact with the bottom surface.

A method for manufacturing a cured product pattern of a curable composition includes the steps of, in sequence, depositing a droplet of the curable composition onto a substrate; bringing a mold having an uneven pattern formed in a surface thereof into contact with the curable composition; curing the curable composition; and releasing a cured product of the curable composition from the mold. The mold has a recess having a bottom surface and a stair structure arranged to form an opening surface that becomes wider from the bottom surface toward the surface of the mold. In the contact step, the curable composition comes into contact with the stair portion after a top of the droplet comes into contact with the bottom surface.

A semiconductor device includes: circuit devices on a first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure on the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate on the upper interconnection structure; gate electrodes between the upper interconnection structure and the second substrate; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode; and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.