A method of manufacturing a non-volatile memory includes the following steps. A stacked structure is formed on a substrate and includes a gate dielectric layer, an assist gate, an insulation layer, and a sacrificial layer stacked in order. A tunneling dielectric layer is formed at one side of the stacked structure. A floating gate is formed on the tunneling dielectric layer. The stacked structure is etched until an uppermost edge of the floating gate is higher than a top surface of the insulation layer. A dielectric material layer is formed to cover sidewalls of the floating gate. The dielectric material layer is etched to form an etched dielectric material layer and expose the uppermost edge of the floating gate. An upper gate structure is formed on the etched dielectric material layer, where a portion of the etched dielectric material layer is disposed between the upper gate structure and the substrate.

A semiconductor device includes a stack structure having gate electrodes and interlayer insulating layers, the stack structure having a cell region and a step region, and the gate electrodes extending in a first direction to have a step shape in the step region, channel structures through the stack structure in the cell region, separation structures through the stack structure and extending in the first direction, and support structures between the separation structures and through the stack structure in the step region. The step region includes first and second regions, the first region closer to the cell region in the first direction than the second region is, the support structures include first and second support structures through the stack structure in the first and second regions, respectively, a maximum width of the first support structure being greater than that of the second support structure.

A semiconductor device includes a stack structure having gate electrodes and interlayer insulating layers, the stack structure having a cell region and a step region, and the gate electrodes extending in a first direction to have a step shape in the step region, channel structures through the stack structure in the cell region, separation structures through the stack structure and extending in the first direction, and support structures between the separation structures and through the stack structure in the step region. The step region includes first and second regions, the first region closer to the cell region in the first direction than the second region is, the support structures include first and second support structures through the stack structure in the first and second regions, respectively, a maximum width of the first support structure being greater than that of the second support structure.

A method for forming a memory device includes providing an initial semiconductor structure, including a base substrate; a first sacrificial layer formed on the base substrate; a stack structure, disposed on the first sacrificial layer; a plurality of channels, formed through the stack structure and the first sacrificial layer; and a gate-line trench, formed through the stack structure and exposing the first sacrificial layer. The method also includes forming at least one protective layer on the sidewalls of the gate-line trench; removing the first sacrificial layer to expose a portion of each of the plurality of channels and the surfaces of the base substrate, using the at least one protective layer as an etch mask; and forming an epitaxial layer on the exposed surfaces of the base substrate and the plurality of channels.

A three-dimensional (3D) semiconductor memory device includes a peripheral logic structure on a substrate and including a peripheral circuits, horizontal semiconductor layers on the peripheral logic structure, a stack structures in which mold layers and electrode pads are alternately stacked in a first direction on the horizontal semiconductor layers, electrode isolation regions separating the stack structures and extending in the first direction and a second direction, the electrode isolation regions being connected to the horizontal semiconductor layers, and through-via structures in the peripheral logic structure. The through-via structures penetrate the stack structures in the first direction. Each of the through-via structures have one side connected to a corresponding one of the through channel contacts. Capacitors are formed by electrode pads respectively with at least one of the electrode isolation regions or with at least one of the through-via structures.

A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

A semiconductor storage device includes: a substrate having a front surface; a plurality of conductive layers arranged in a first direction, the first direction intersecting the front surface of the substrate; a plurality of memory cells connected to the plurality of conductive layers; a contact electrode extending in the first direction and connected to one of the plurality of conductive layers; and an insulating structure extending in the first direction, the insulating structure connected to an end portion of the contact electrode on one side of the contact electrode in the first direction, and penetrating the plurality of conductive layers.

A semiconductor device including a substrate that includes a cell array region and a peripheral circuit region; a cell transistor on the cell array region of the substrate; a peripheral transistor on the peripheral circuit region of the substrate; a first interconnection layer connected to the cell transistor; a second interconnection layer connected to the peripheral transistor; an interlayer dielectric layer covering the first interconnection layer; and a blocking layer spaced apart from the first interconnection layer, the blocking layer covering a top surface and a sidewall of the second interconnection layer.

In a semiconductor storage device including a plurality of memory cells formed at a laminated substrate including a support layer, an insulating layer on the support layer, and a semiconductor layer on the insulating layer, the plurality of memory cells each include a floating gate transistor and a selection transistor. The floating gate transistor includes a first source region, a first drain region, a first body region, a first body contact region, a floating gate insulating film, and a floating gate electrode, and the selection transistor includes a second source region, a second drain region, a second body region, a second body contact region insulated from the first body contact region, a selection gate insulating film, and a selection gate electrode.