A method for producing a 3D memory device including: providing a first level including a single crystal layer and control circuits, where the control circuits include a plurality of first transistors; forming at least one second level above the first level; performing a first etch step including etching holes within the second level; performing processing steps to form a plurality of first memory cells within the second level, where each of the first memory cells include one of a plurality of second transistors, where the control circuits include memory peripheral circuits, where at least one first memory cell is at least partially atop a portion of the memory peripheral circuits, and where fabrication processing of the first transistors accounts for a temperature and time associated with processing the second level and the plurality of second transistors by adjusting a process thermal budget of the first level accordingly.

A three-dimensional AND flash memory device includes a stack structure, isolators, channel pillars, source pillars and drain pillars, and charge storage structures. The stack structure is located on a dielectric substrate and includes gate layers and insulating layers alternately stacked with each other. The isolators divide the stack structure into sub-blocks and include walls and slits. The walls include isolation layers and the insulating layers stacked alternately with each other, and the isolation layers are buried in the gate layers. The slits alternate with the walls, and each of the slits extends through the stack structure. The channel pillars extend through the stack structure in each of the sub-blocks. The source pillars and the drain pillars are located in the channel pillars. The charge storage structures are located between the gate layers and the channel pillar.

A 3D semiconductor device, the device including: a first level including a first single crystal layer, the first level including first transistors, where the first transistors each include a single crystal channel; first metal layers interconnecting at least the first transistors; a second metal layer overlaying the first metal layers; and a second level including a second single crystal layer, the second level including second transistors, where the second level overlays the first level, where the second transistors each include at least two side-gates, where the second level is bonded to the first level, and where the bonded includes oxide to oxide bonds.

A method for producing a 3D semiconductor device including: providing a first level including a first single crystal layer; forming peripheral circuitry in and/or on the first level, and includes first single crystal transistors; forming a first metal layer on top of the first level; forming a second metal layer on top of the first metal layer; forming second level disposed on top of the second metal layer; performing a first lithography step; forming a third level on top of the second level; performing a second lithography step; processing steps to form first memory cells within the second level and second memory cells within the third level, where the plurality of first memory cells include at least one second transistor, and the plurality of second memory cells include at least one third transistor; and deposit a gate electrode for second and third transistors simultaneously.

A semiconductor memory device according to an embodiment includes a substrate, a lower interconnect, a source line, word lines, a pillar, a pattern portion, a contact. The source line is provided in a first layer above the lower interconnect. The pattern portion is provided to be separated and insulated from the source line in the first layer. A contact is extending in a first direction, penetrating the pattern portion, and provided on the lower interconnect. A width of the contact in a second direction parallel to a surface of the substrate differs between a portion above a boundary plane that is included in the first layer and is parallel to the surface of the substrate, and a portion below the boundary plane.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

A semiconductor device includes a stack structure including a gate stack region and dummy stack region. The gate stack region includes interlayer insulating layers and gate electrodes alternately stacked. The dummy stack region includes dummy insulating layers and dummy horizontal layers alternately stacked. A separation structure penetrates the stack structure. A vertical memory structure penetrates the gate stack region in a first region. A plurality of gate contact structures electrically connect to the gate electrodes in a second region. The gate electrodes include a first gate electrode and a second gate electrode disposed on a level higher than the first gate electrode. Each of the gate contact structures includes a gate contact plug and a first insulating spacer. The gate contact plugs include a first gate contact plug penetrating the second gate electrode and contacting the first gate electrode, and a second gate contact plug contacting the second gate electrode.

A semiconductor device includes a stack structure including a gate stack region and dummy stack region. The gate stack region includes interlayer insulating layers and gate electrodes alternately stacked. The dummy stack region includes dummy insulating layers and dummy horizontal layers alternately stacked. A separation structure penetrates the stack structure. A vertical memory structure penetrates the gate stack region in a first region. A plurality of gate contact structures electrically connect to the gate electrodes in a second region. The gate electrodes include a first gate electrode and a second gate electrode disposed on a level higher than the first gate electrode. Each of the gate contact structures includes a gate contact plug and a first insulating spacer. The gate contact plugs include a first gate contact plug penetrating the second gate electrode and contacting the first gate electrode, and a second gate contact plug contacting the second gate electrode.

A method, non-transitory computer readable medium and an evaluation system for evaluating an intermediate product related to a three dimensional NAND memory unit. The evaluation system may include an imager and a processing circuit. The imager may be configured to obtain, via an open gap, an electron image of a portion of a structural element that belongs to an intermediate product. The structural element may include a sequence of layers that include a top layer that is followed by alternating nonconductive layers and recessed conductive layers. The imager may include electron optics configured to scan the portion of the structural element with an electron beam that is oblique to a longitudinal axis of the open gap. The processing circuit is configured to evaluate the intermediate product based on the electron image. The open gap (a) exhibits a high aspect ratio, (b) has a width of nanometric scale, and (c) is formed between structural elements of the intermediate product.