A memory device includes a first semiconductor structure and a second semiconductor structure. The memory device further includes a bonding structure between the first semiconductor structure and the second semiconductor structure, the bonding structure comprising a first bonding pattern and a second bonding pattern in contact with each other, the first semiconductor structure being electrically connected with the second semiconductor structure through the bonding structure. The memory device further includes a shielding structure between the first semiconductor structure and the second semiconductor structure and surrounding the bonding structure, the shielding structure comprising a third bonding pattern and a fourth bonding pattern in contact with each other, the shielding structure being electrically connected with a biased voltage.

A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

A three-dimensional semiconductor device includes a first substrate; a plurality of first transistors on the first substrate; a second substrate on the plurality of first transistors; a plurality of second transistors on the second substrate; and an interconnection portion electrically connecting the plurality of first transistors and the plurality of second transistors. Each of the plurality of first transistors includes a first gate insulating film on the first substrate and having a first hydrogen content. Each of the plurality of second transistors includes a second gate insulating film on the second substrate and having a second hydrogen content. The second hydrogen content is greater than the first hydrogen content.

A plasma treatment chamber comprises one or more sidewalls. A support surface within the one or more sidewalls holds a workpiece. A first gas injector along the one or more sidewalls injects a first gas flow in a first direction generally parallel to and across a surface of the workpiece. A first pump port along the one or more sidewalls generally opposite of the first gas injector pumps out the first gas flow. A second gas injector along the one or more sidewalls injects a second gas flow in a second direction generally parallel to and across the surface of the workpiece. A second pump port along the one or more sidewalls generally opposite of the second gas injector pumps out the second gas flow. Conductance control rings modulate conductance of the pump ports and are located proximate to plasma screens at a top of the pump ports.

In certain aspects, a three-dimensional (3D) memory device includes a single crystalline silicon layer, a polysilicon layer, a transistor in contact with the single crystalline silicon layer, and a channel structure in contact with the polysilicon layer. The polysilicon layer and the single crystalline silicon layer are nonoverlapping and at least partially noncoplanar.

In certain aspects, a three-dimensional (3D) memory device includes a single crystalline silicon layer, a polysilicon layer, a transistor in contact with the single crystalline silicon layer, and a channel structure in contact with the polysilicon layer. The polysilicon layer and the single crystalline silicon layer are nonoverlapping and at least partially noncoplanar.

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A transistor is formed in a first region on a first side of a single crystalline silicon substrate. A step layer is formed in a second region on the first side of the single crystalline silicon substrate. A channel structure extending through a stack structure and in contact with the step layer is formed. The stack structure includes interleaved dielectric layers and conductive layers on the step layer. Part of the single crystalline silicon substrate that is in the second region is removed from a second side opposite to the first side of the single crystalline silicon substrate to expose the step layer from the second side.

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A transistor is formed in a first region on a first side of a single crystalline silicon substrate. A step layer is formed in a second region on the first side of the single crystalline silicon substrate. A channel structure extending through a stack structure and in contact with the step layer is formed. The stack structure includes interleaved dielectric layers and conductive layers on the step layer. Part of the single crystalline silicon substrate that is in the second region is removed from a second side opposite to the first side of the single crystalline silicon substrate to expose the step layer from the second side.

A 3D integrated circuit, the circuit including: a first level including a first wafer, the first wafer including a first crystalline substrate, a plurality of first transistors, and first copper interconnecting layers, where the first copper interconnecting layers at least interconnect the plurality of first transistors; and a second level including a second wafer, the second wafer including a second crystalline substrate, a plurality of second transistors, and second copper interconnecting layers, where the second copper interconnecting layers at least interconnect the plurality of second transistors, where the second level is bonded to the first level, where the bonded includes metal to metal bonding, where the bonded includes oxide to oxide bonding, and where at least one of the second transistors include a replacement gate.

A semiconductor memory device according to an embodiment includes a semiconductor substrate, a first insulating layer, a second insulating layer, the first insulating layer between the semiconductor substrate and the second insulating layer, a semiconductor layer between the first insulating layer and the second insulating layer, the semiconductor layer extending in a first direction parallel to a surface of the semiconductor substrate, a gate electrode layer extending in a direction perpendicular to the surface; a first insulating film between the semiconductor layer and the gate electrode layer, a second insulating film between the first insulating film and the gate electrode layer the second insulating film in contact with the first insulating layer and the second insulating layer, a polycrystalline silicon region between the first insulating film and the second insulating film; and a metal film between the polycrystalline silicon region and the second insulating film containing titanium and silicon.