A semiconductor memory device according to an embodiment includes a memory cell array and a contact unit. The contact unit connects the memory cell array to a conductive layer and a contact. The contact unit includes a descending unit and an ascending unit. The descending unit includes a plurality of terrace parts descending in a first direction away from the memory cell array. The ascending unit is adjacent to the descending unit in a second direction perpendicular to the first direction. The ascending unit includes a plurality of terrace parts ascending in the first direction. The contact arranged in the terrace part of the descending unit and the contact arranged in the terrace part of the ascending unit are arranged in the second direction.

A semiconductor device includes a stacked film including a plurality of electrode layers and a plurality of insulating layers alternately stacked in a first direction and a columnar portion including a charge storage layer and a first semiconductor layer and extending in the first direction in the stacked film. The device further includes a second semiconductor layer provided on the stacked film and the columnar portion, and at least a part of regions in the second semiconductor layer contains phosphorus having an atomic concentration of 1.0×10.sup.21/cm.sup.3 or more and hydrogen having an atomic concentration of 1.0×10.sup.19/cm.sup.3 or less.

A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a charge storage layer between the semiconductor layer and the first gate electrode layer, the charge storage layer containing a first element, a second element, and oxygen, the first element being at least one element selected from the group consisting of hafnium and zirconium, and the second element being at least one element selected from the group consisting of nitrogen and aluminum; a first insulating layer between the charge storage layer and the first gate electrode layer; and a second insulating layer between the semiconductor layer and the first gate electrode layer, the second insulating layer containing silicon and nitrogen, the second insulating layer surrounding the charge storage layer in a cross section that being parallel to the first direction and including the charge storage layer.

A semiconductor device and method for manufacturing the semiconductor device are disclosed. Specifically, the semiconductor device may include a charge trapping layer with improved retention and speed for VNAND applications. The charge trapping layer may comprise an aluminum nitride (AlN) or aluminum oxynitride (AlON) layer.

Provided are memory devices and memory systems. The memory device includes a memory cell array in a first semiconductor layer and including word lines stacked in a first direction, and channel structures passing through the word lines in the first direction; a control logic circuit in a second semiconductor layer located below the first semiconductor layer in the first direction; and a physical unclonable function (PUF) circuit including a plurality of through electrodes passing through the first semiconductor layer and the second semiconductor layer, and configured to generate PUF data according to resistance values of the plurality of through electrodes, and generate the PUF data based on a node voltage between through electrodes connected in series, among the plurality of through electrodes.

Techniques herein include methods of forming circuits by combining multiple substrates. High voltage devices are fabricated on a first wafer, and low voltage devices and/or memory are then fabricated on a second wafer and/or third wafer.

A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.

The present disclosure may provide a semiconductor device having a stable structure and a low manufacturing degree of the difficulty. The device may include conductive layers and insulating layers which are alternately stacked; a plurality of pillars passing through the conductive layers and the insulating layers; and a plurality of deposition inhibiting patterns, each deposition inhibiting pattern being formed along a portion of an interface between a side-wall of each of the pillars and each of the conductive layers and along a portion of an interface between each of the insulating layers and each of the conductive layers.

A semiconductor device according to one embodiment includes: a semiconductor substrate; a peripheral circuit provided on the semiconductor substrate; and a stacked body provided above the peripheral circuit, which has a memory cell array. The peripheral circuit includes: a metal film including silicon; a silicide film stacked on the metal film; and a barrier metal film stacked on the silicide film.