A non-volatile memory device and its manufacturing method are provided. The non-volatile memory device includes a substrate and a plurality of first gate structures and a plurality of second gate structures formed on the substrate. The substrate includes a center region and two border regions located on opposite sides of the center region. The center region and two border regions are located in an array region. The first gate structures are located in the center region, and the second gate structures are located in one of the border regions. Each of the first gate structures has a first width, and each of the second gate structures has a second width less than the first width. There is a first spacing between the first gate structures, and there is a second spacing which is greater than the first spacing between the second gate structures.

Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

An NVM device includes a semiconductor substrate, a first floating gate, a first control gate, a first drain region, and a common source region. The semiconductor substrate has a recess extending downward from the substrate surface. The first floating gate is disposed in the recess, has a base and a side wall connecting to the base. The first control gate is disposed on and adjacent to the first floating gate. The first drain region is disposed in the semiconductor substrate in the recess. The common source region is formed in the semiconductor substrate in the recess, is adjacent to the first floating gate, and includes a main body and an extension part. The main body is disposed below a bottom surface of the recess and adjacent to the base. The extension part extends upward from the bottom surface beyond the base to be adjacent to the side wall.

Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

Various embodiments of the present disclosure are directed towards a method for opening a source line in a memory device. An erase gate line (EGL) and the source line are formed elongated in parallel. The source line underlies the EGL and is separated from the EGL by a dielectric layer. A first etch is performed to form a first opening through the EGL and stops on the dielectric layer. A second etch is performed to thin the dielectric layer at the first opening, wherein the first and second etches are performed with a common mask in place. A silicide process is performed to form a silicide layer on the source line at the first opening, wherein the silicide process comprises a third etch with a second mask in place and extends the first opening through the dielectric layer. A via is formed extending through the EGL to the silicide layer.

A manufacturing method of a memory device are provided. The method includes following steps. A gate stacking structure is formed over a substrate. A first insulating layer, a second insulating layer and a mask material layer are sequentially formed over the substrate to cover the gate stacking structure. An ion implantation process is performed on the mask material layer to form a doped portion in the mask material layer. The doped portion caps on a top portion of the gate stacking structure. A first patterning process is performed on the mask material layer using the doped portion as a shadow mask to remove a bottom portion of the mask material layer extending along a surface of the substrate. A second patterning process is performed to remove the doped portion of the mask material layer and an exposed bottom portion of the second insulating layer surrounding the gate stacking structure.

Disclosed is a floating gate memristor device comprising: a substrate; a floating gate disposed on the substrate; an insulating layer covering the floating gate; a first electrode including a plurality of control terminals disposed on the insulating layer and spaced apart from each other, wherein the plurality of control terminals vertically overlap the floating gate; a second electrode spaced away from the first electrode, wherein a ground voltage is applied to the second electrode; and a third electrode disposed on the substrate and electrically connected to the floating gate.

In an embodiment a memory cell includes a first doped well of a first conductivity type in contact with a second doped well of a second conductivity type, the second conductivity type being opposite to the first conductivity type, a third doped well of the second conductivity type in contact with a fourth doped well of the first conductivity type, a first wall in contact with the second and fourth wells, the first wall including a conductive or semiconductor core and an insulating sheath, a stack of layers including a first insulating layer, a first semiconductor layer, a second insulating layer and a second semiconductor layer at least partially covering the second and fourth wells and a third semiconductor layer located below the second and fourth wells and the first wall.

The present disclosure relates to an integrated chip comprising a substrate having a first pair of opposing sidewalls that define a trench. The trench extends into a front-side surface of the substrate. A first source/drain region is disposed along the front-side surface of the substrate. A second source/drain region is disposed along the front-side surface of the substrate. A gate structure is disposed within the trench and is arranged laterally between the first source/drain region and the second source/drain region. The gate structure extends along the first pair of opposing sidewalls to an upper surface of the substrate. A bottom surface of the gate structure is disposed below a bottom surface of the first source/drain region.