Various embodiments of the present application are directed towards an integrated memory chip with an enhanced device-region layout for reduced leakage current and an enlarged word-line etch process window (e.g., enhanced word-line etch resiliency). In some embodiments, the integrated memory chip comprises a substrate, a control gate, a word line, and an isolation structure. The substrate comprises a first source/drain region. The control gate and the word line are on the substrate. The word line is between and borders the first source/drain region and the control gate and is elongated along a length of the word line. The isolation structure extends into the substrate and has a first isolation-structure sidewall. The first isolation-structure sidewall extends laterally along the length of the word line and underlies the word line.

Various embodiments of the present application are directed towards an integrated memory chip comprising a memory array with a strap-cell architecture that reduces the number of distinct strap-cell types and that reduces strap-line density. In some embodiments, the memory array is limited to three distinct types of strap cells: a source line/erase gate (SLEG) strap cell; a control gate/word line (CGWL) strap cell; and a word-line strap cell. The small number of distinct strap-cell types simplifies design of the memory array and further simplifies design of a corresponding interconnect structure. Further, in some embodiments, the three distinct strap-cell types electrically couple word lines, erase gates, and control gates to corresponding strap lines in different metallization layers of an interconnect structure. By spreading the strap lines amongst different metallization layers, strap-line density is reduced.

Embodiments of 3D memory devices and methods for forming the same are disclosed. In an example, a 3D memory device includes a substrate having a first side and a second side opposite to the first side. The 3D memory device also includes a memory stack including interleaved conductive layers and dielectric layers at the first side of the substrate. The 3D memory device also includes a plurality of channel structures each extending vertically through the memory stack. The 3D memory device also includes a first insulating structure extending vertically through the memory stack and extending laterally to separate the plurality of channel structures into a plurality of blocks. The 3D memory device further includes a first doped region in the substrate and in contact with the first insulating structure. The 3D memory device further includes a first contact extending vertically from the second side of the substrate to be in contact with the first doped region.

A semiconductor device includes a peripheral circuit region comprising a first substrate, circuit elements on the first substrate, a first insulating layer covering the circuit elements, and a contact plug passing through the first insulating layer and disposed to be connected to the first substrate; and a memory cell region comprising a second substrate, gate electrodes on the second substrate and stacked in a vertical direction, and channel structures passing through the gate electrodes, wherein the contact plug comprises a metal silicide layer disposed to contact the first substrate and having a first thickness, a first metal nitride layer on the metal silicide layer to contact the metal silicide layer and having a second thickness, greater than the first thickness, a second metal nitride layer on the first metal nitride layer, and a conductive layer on the second metal nitride layer.

The present disclosure provides a semiconductor memory device and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor memory device includes a substrate, a source structure, a laminated structure, a floating body, a trench region, a drain structure and a gate structure. The source structure is formed on the substrate. The laminated structure includes a nitride layer and an oxide layer that are alternately laminated on the source structure. The floating body is formed in the oxide layer, and a through hole is formed in the floating body along a lamination direction of the laminated structure. The trench region is formed inside the floating body, a through hole is also formed in the trench region along the lamination direction, and the trench region is in contact with the source structure.

A nonvolatile memory device includes a cell array formed on a substrate, and a control gate pickup structure, wherein the cell array comprises floating gates, and a control gate surrounding the floating gates, wherein the control gate pickup structure comprises a floating gate polysilicon layer, a control gate polysilicon layer surrounding the floating gate polysilicon layer and connected to the control gate, and at least one contact plug formed on the control gate polysilicon layer.

An integrated circuit includes first and second active regions, first and second standard cells on the first active region and the second active region, and a filler cell between the first and second standard cells and including first and second insulating isolations. The filler cell has a one-pitch dimension. The first and second insulating isolations are spaced the one-pitch dimension apart from each other. The first insulating isolation of the filler cell is disposed at a first boundary between the first standard cell and the filler cell. The second insulating isolation of the filler cell is disposed at a second boundary between the second standard cell and the filler cell. The first and second insulating isolations separate at least a part of the first active region, and at least a part of the second active region.

Provided is a semiconductor device. The semiconductor device includes a floating gate disposed on a substrate; a memory gate disposed on the floating gate; a first spacer disposed sidewalls of the floating gate and the memory gate, and an upper surface of the substrate; a second spacer disposed on the first spacer; a select high-k film disposed on a first portion of a sidewall of the first spacer between the substrate and the second spacer; and a select gate disposed on a second portion of the sidewall of the first spacer between the substrate and the second spacer. A width of a portion of the first spacer is reduced as a distance to the substrate decreases, and the portion of the first spacer is disposed between the substrate and the second spacer.

A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

A method includes disposing a layer stack on a substrate, the layer stack including a number of levels. A first control gate structure is formed in a first level of the number of levels by: forming a first opening through a dielectric layer of the first level and a sacrificial layer of the first level; removing a remaining portion of the sacrificial layer of the first level to form a first cavity; and disposing a first conductive layer in the first cavity. A second control gate structure is formed in a second level below the first level by: extending the first opening into a dielectric layer of the second level and a sacrificial layer of the second level to form a second opening; removing a remaining portion of the sacrificial layer of the second level to form a second cavity; and disposing a second conductive layer in the second cavity.