A memory device includes a substrate, a first transistor, a second transistor, and a capacitor. The first transistor is over the substrate and includes a select gate. The second transistor is over the substrate and connected to the first transistor in series, in which the second transistor includes a floating gate. The capacitor is over the substrate and connected to the second transistor, wherein the capacitor includes a top electrode, a bottom electrode in the substrate, and an insulating layer between the top electrode and the bottom electrode. The insulating layer includes nitrogen. A nitrogen concentration of the insulating layer increases in a direction from the top electrode to the bottom electrode.

The present application discloses a semi-floating gate device. A floating gate structure covers a selected area of a first well region and is used to form a conductive channel. The floating gate structure further covers a surface of a lightly doped drain region, and a floating gate material layer and the lightly doped drain region contact at a dielectric layer window to form a PN structure. A source region is self-aligned with a first side surface of the floating gate structure. A first control gate is superposed on a top of the floating gate structure. A second control gate is disposed on a surface of the lightly doped drain region between the drain region and a second side surface of the floating gate structure. The first control gate and the second control gate are isolated by an inter-gate dielectric layer.

A multiple input device is disclosed. The multiple input device includes a semiconductor structure extending in a first direction, a first dielectric material surrounding a portion of the semiconductor structure, a floating gate on the first dielectric material and surrounding the portion of the semiconductor structure, and a second dielectric material on the floating gate and surrounding the portion of the semiconductor structure. The multiple input device also includes a plurality of control gates on the second dielectric material. At least one of the control gates extends vertically away from the semiconductor structure in a second direction and at least one of the control gates extends vertically away from the semiconductor structure in a third direction.

A nonvolatile memory device is provided. The device comprises a memory transistor. A first capacitor is coupled to the memory transistor. A second capacitor is coupled to the memory transistor. The second capacitor comprises a first electrode and a second electrode. The first capacitor and the second capacitor are connected to separate input terminals.

A bipolar transistor includes a common collector region comprising a buried semiconductor layer and an annular well. A well region is surrounded by the annular well and delimited by the buried semiconductor layer. A first base region and a second base region are formed by the well region and separated from each other by a vertical gate structure. A first emitter region is implanted in the first base region, and a second emitter region is implanted in the second base region. A conductor track electrically couples the first emitter region and the second base region to configure the bipolar transistor as a Darlington-type device. Structures of the bipolar transistor may be fabricated in a co-integration with a non-volatile memory cell.

In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.

Various embodiments of the present application are directed to an IC, and associated forming methods. In some embodiments, the IC comprises a memory region and a logic region integrated in a substrate. A plurality of memory cell structures is disposed on the memory region. Each memory cell structure of the plurality of memory cell structures comprises a control gate electrode disposed over the substrate, a select gate electrode disposed on one side of the control gate electrode, and a spacer between the control gate electrode and the select gate electrode. A contact etch stop layer (CESL) is disposed along an upper surface of the substrate, extending upwardly along and in direct contact with a sidewall surface of the select gate electrode within the memory region. A lower inter-layer dielectric layer is disposed on the CESL between the plurality of memory cell structures within the memory region.

A non-volatile memory device is provided. The non-volatile memory device includes a substrate, a floating gate, and a gate. The substrate includes a source region and a drain region, and a channel region between the source region and the drain region. The floating gate is over the channel region. The floating gate includes a first conductive layer and a second conductive layer underlying the first conductive layer. The gate is adjacent to the floating gate.

The present disclosure describes a patterning process for a strap region in a memory cell for the removal of material between polysilicon lines. The patterning process includes depositing a first hard mask layer in a divot formed on a top portion of a polysilicon layer interposed between a first polysilicon gate structure and a second polysilicon gate; depositing a second hard mask layer on the first hard mask layer. The patterning process also includes performing a first etch to remove the second hard mask layer and a portion of the second hard mask layer from the divot; performing a second etch to remove the second hard mask layer from the divot; and performing a third etch to remove the polysilicon layer not covered by the first and second hard mask layers to form a separation between the first polysilicon gate structure and the second polysilicon structure.

A neuromorphic device for the analog computation of a linear combination of input signals, for use, for example, in an artificial neuron. The neuromorphic device provides non-volatile programming of the weights, and fast evaluation and programming, and is suitable for fabrication at high density as part of a plurality of neuromorphic devices. The neuromorphic device is implemented as a vertical stack of flash-like cells with a common control gate contact and individually contacted source-drain (SD) regions. The vertical stacking of the cells enables efficient use of layout resources.