A semiconductor memory device according to an embodiment includes a substrate, a lower interconnect, a source line, word lines, a pillar, a pattern portion, a contact. The source line is provided in a first layer above the lower interconnect. The pattern portion is provided to be separated and insulated from the source line in the first layer. A contact is extending in a first direction, penetrating the pattern portion, and provided on the lower interconnect. A width of the contact in a second direction parallel to a surface of the substrate differs between a portion above a boundary plane that is included in the first layer and is parallel to the surface of the substrate, and a portion below the boundary plane.

A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

A 3D semiconductor device, the device comprising: a first level comprising a first single crystal layer, said first level comprising first transistors, wherein each of said first transistors comprises a single crystal channel; first metal layers interconnecting at least said first transistors; a second metal layer overlaying said first metal layers; and a second level comprising a second single crystal layer, said second level comprising second transistors, wherein said second level overlays said first level, wherein at least one of said second transistors comprises a gate all around structure, wherein said second level is directly bonded to said first level, and wherein said bonded comprises direct oxide to oxide bonds.

There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stack comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers, a plurality of step-shaped grooves defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap-fill insulating pattern filling the plurality of step-shaped grooves, a second gap-fill insulating pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.

There are provided a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device includes a gate stack comprising a plurality of first interlayer insulating patterns and a plurality of conductive patterns alternately stacked a dummy stack comprising a plurality of second interlayer insulating patterns and a plurality of sacrificial insulating layers, a plurality of step-shaped grooves defined at different depths in the gate stack, a plurality of openings passing through the dummy stack and spaced apart from each other, a first gap-fill insulating pattern filling the plurality of step-shaped grooves, a second gap-fill insulating pattern filling the plurality of openings, a plurality of conductive gate contacts passing through the first gap-fill insulating pattern and connected to the plurality of conductive patterns, and a plurality of conductive peripheral circuit contacts passing through the second gap-fill insulating pattern.

A semiconductor device includes a stack structure including a gate stack region and dummy stack region. The gate stack region includes interlayer insulating layers and gate electrodes alternately stacked. The dummy stack region includes dummy insulating layers and dummy horizontal layers alternately stacked. A separation structure penetrates the stack structure. A vertical memory structure penetrates the gate stack region in a first region. A plurality of gate contact structures electrically connect to the gate electrodes in a second region. The gate electrodes include a first gate electrode and a second gate electrode disposed on a level higher than the first gate electrode. Each of the gate contact structures includes a gate contact plug and a first insulating spacer. The gate contact plugs include a first gate contact plug penetrating the second gate electrode and contacting the first gate electrode, and a second gate contact plug contacting the second gate electrode.

A semiconductor device includes a stack structure including a gate stack region and dummy stack region. The gate stack region includes interlayer insulating layers and gate electrodes alternately stacked. The dummy stack region includes dummy insulating layers and dummy horizontal layers alternately stacked. A separation structure penetrates the stack structure. A vertical memory structure penetrates the gate stack region in a first region. A plurality of gate contact structures electrically connect to the gate electrodes in a second region. The gate electrodes include a first gate electrode and a second gate electrode disposed on a level higher than the first gate electrode. Each of the gate contact structures includes a gate contact plug and a first insulating spacer. The gate contact plugs include a first gate contact plug penetrating the second gate electrode and contacting the first gate electrode, and a second gate contact plug contacting the second gate electrode.

Embodiments of three-dimensional (3D) memory devices with a 3D NAND memory array having a plurality of pages, an on-die cache coupled to the memory array on a same chip and configured to cache a plurality of batches of program data between a host and the memory array, the on-die cache having SRAM cells, and a controller coupled to the on-die cache on the same chip. The controller is configured to check a status of an (N−2).sup.th batch of program data, N being an integer equal to or greater than 2, program an (N−1).sup.th batch of program data into respective pages in the 3D NAND memory array, and cache an N.sup.th batch of program data in respective space in the on-die cache as a backup copy of the N.sup.th batch of program data.

A method for fabricating a semiconductor device includes: forming a first gate dielectric layer in a first and a second regions of a peripheral region of a substrate; forming a first conductive layer and a first hard mask layer over the substrate; forming a first mask layer on the first hard mask layer in the first region; removing the first hard mask layer outside the first region; removing the first hard mask layer; performing a wet etch process by taking the first hard mask layer as a mask, and removing the first conductive layer and the first gate dielectric layer outside the first region; removing the first hard mask layer and the first conductive layer; forming a second gate dielectric layer in the second region; and forming a first and a second gate conductive layers in the first and the second regions respectively.