A semiconductor device and a method for fabricating the same are disclosed. A substrate including a first device region and a second device region is provided. A first isolation structure is formed in the substrate of the first device region and a second isolation structure is formed in the substrate of the second device region. Ion implantation on the first isolation structure is performed. The first isolation structure and the second isolation structure are etched back to form a first recess in the first isolation structure and a second recess in the second isolation structure.

A semiconductor device with high storage capacity is provided. The semiconductor device includes first to sixth insulators, first to third conductors, and first to third material layers. The first conductor overlaps with a first insulator and a first material layer. A first region of the first material layer overlaps with a second material layer, a second conductor, a second insulator, and a third insulator. The third material layer is positioned in a region including a second region of the first material layer and top surfaces of the second material layer, the second conductor, the second insulator, and the third insulator; a fourth insulator is positioned over the third material layer; the sixth insulator is positioned over the fourth insulator; and a fifth insulator is positioned over the sixth insulator. The third conductor is positioned over the fifth insulator overlapping with the second region of the first material layer. The first to third material layers include oxide containing indium, an element M (M is aluminum, gallium, tin, or titanium), and zinc.

A nonvolatile memory device includes; a memory cell area including a common source plate, at least one cell structure under the common source plate, and a first metal pad under the at least one cell structure, and a peripheral circuit area on which the memory cell area is mounted, including a middle area , a first edge area, and a second metal pad on the first edge area. The memory cell area further includes a first contact extending from the common source plate and connected to the first metal pad. The peripheral circuit area further includes a second contact extending from a common source line switch and connected to the second metal pad. The first metal pad contacts with the second metal pad on the second metal pad.

A nonvolatile memory device includes; a memory cell area including a common source plate, at least one cell structure under the common source plate, and a first metal pad under the at least one cell structure, and a peripheral circuit area on which the memory cell area is mounted, including a middle area , a first edge area, and a second metal pad on the first edge area. The memory cell area further includes a first contact extending from the common source plate and connected to the first metal pad. The peripheral circuit area further includes a second contact extending from a common source line switch and connected to the second metal pad. The first metal pad contacts with the second metal pad on the second metal pad.

A semiconductor device includes a substrate that includes a cell array region, a peripheral region, and a scribe lane region. A stack structure is disposed on the cell array region of the substrate and includes electrodes that are vertically stacked and spaced apart from each other. A dummy structure extends from the peripheral region to the scribe lane region of the substrate and includes first dielectric layers and second dielectric layers that are alternately and repeatedly stacked. A vertical channel structure penetrates the stack structure, and a slit in the dummy structure on the scribe lane region. The slit extends in a direction that is perpendicular to a top surface of the substrate and penetrates at least a portion of the dummy structure. The slit includes a void.

A semiconductor device includes a substrate that includes a cell array region, a peripheral region, and a scribe lane region. A stack structure is disposed on the cell array region of the substrate and includes electrodes that are vertically stacked and spaced apart from each other. A dummy structure extends from the peripheral region to the scribe lane region of the substrate and includes first dielectric layers and second dielectric layers that are alternately and repeatedly stacked. A vertical channel structure penetrates the stack structure, and a slit in the dummy structure on the scribe lane region. The slit extends in a direction that is perpendicular to a top surface of the substrate and penetrates at least a portion of the dummy structure. The slit includes a void.

A semiconductor device includes a memory region including an array of memory cell devices, and a test region including a test memory cell structure. The test memory cell structure includes a first gate stack on a first raised portion of a substrate, a first polysilicon structure adjacent to the first raised portion and in a region between the first raised portion and a second raised portion of the substrate, a first spacer adjacent to the first polysilicon structure, and a second gate stack on the second raised portion, a second polysilicon structure adjacent to the second raised portion and in the region between the first raised portion and the second raised portion, and a second spacer adjacent to the second polysilicon structure. The semiconductor device includes an interlayer dielectric layer over at least a portion of the memory region and at least a portion of the test region.

Embodiments of bonded unified semiconductor chips and fabrication and operation methods thereof are disclosed. In an example, a method for forming a unified semiconductor chip is disclosed. A first semiconductor structure is formed. The first semiconductor structure includes one or more processors, an array of embedded DRAM cells, and a first bonding layer including a plurality of first bonding contacts. A second semiconductor structure is formed. The second semiconductor structure includes an array of NAND memory cells and a second bonding layer including a plurality of second bonding contacts. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the first bonding contacts are in contact with the second bonding contacts at a bonding interface.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first semiconductor structure and the second semiconductor structure. The first semiconductor structure includes a peripheral circuit. The second semiconductor structure includes an array of memory cells, and a plurality of bit lines coupled to the memory cells and each extending in a second direction perpendicular to the first direction. Each of the memory cells includes a vertical transistor extending in a first direction, and a storage unit coupled to the vertical transistor. The vertical transistor includes a semiconductor body extending in the first direction, and a gate structure in contact with a plurality of sides of the semiconductor body. One end of the semiconductor body coupled to the storage unit is flush with the gate structure. A respective one of the bit lines and a respective storage unit are coupled to opposite ends of each one of the memory cells in the first direction. The array of memory cells is coupled to the peripheral circuit across the bonding interface.

A semiconductor device includes a lower stepped connection part at a first vertical level on a substrate, an upper stepped connection part at a second vertical level higher than the first vertical level on the substrate, a lower insulating block contacting each of the plurality of lower conductive pad parts at the first vertical level, an upper insulating block contacting each of the plurality of upper conductive pad parts at the second vertical level, an intermediate insulating film between the lower insulating block and the upper insulating block at a third vertical level between the first and second vertical levels, and a first plug structure extending into the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction, wherein a width of the first plug structure in the horizontal direction is greatest at the third vertical level.