A memory device includes a first cell array region and a second cell array region separated by a separation region, each including at least one memory block having a plurality of gate electrode layers stacked in a first direction. The gate electrode layers include an upper select electrode layer including a plurality of string select lines, and a first electrode layer including a plurality of first word lines arranged below the string select lines. The first word lines include a first connection line to connect first end portions of the first word lines positioned on the opposite side of the separation region to each other and a plurality of second connection lines to connect some of second end portions of the plurality of first word lines adjacent to the separation region to each other, wherein each of the second connection lines is shorter than the first connection line.

A memory device includes a first cell array region and a second cell array region separated by a separation region, each including at least one memory block having a plurality of gate electrode layers stacked in a first direction. The gate electrode layers include an upper select electrode layer including a plurality of string select lines, and a first electrode layer including a plurality of first word lines arranged below the string select lines. The first word lines include a first connection line to connect first end portions of the first word lines positioned on the opposite side of the separation region to each other and a plurality of second connection lines to connect some of second end portions of the plurality of first word lines adjacent to the separation region to each other, wherein each of the second connection lines is shorter than the first connection line.

A method of manufacturing a semiconductor device includes forming a molded structure of stacked and alternating interlayer insulating layers and sacrificial layers on a lower structure, forming a hole through the molded structure, forming recess regions in the sacrificial layers of the molded structure, respectively, by removing a portion of the sacrificial layers, exposed through the hole, from side surfaces of the sacrificial layers, sequentially forming a preliminary blocking pattern and a charge storage pattern in each of the recess regions, sequentially forming a tunneling layer and a channel layer in the hole, forming trenches penetrating through the molded structure, such that the trenches extend in a line shape, removing the sacrificial layers exposed by the trenches, such that the preliminary blocking pattern is exposed, and oxidizing the preliminary blocking pattern, after removing the sacrificial layers, such that a blocking pattern is formed.

Aspects of the disclosure provide a semiconductor device. In some examples, the semiconductor device includes a seal ring structure surrounding the region. The seal ring structure includes a first wall structure that extends through the silicon layer, and a first length of the first wall structure along a side periphery of the first die is longer than a pitch of contact structures.

In a method for fabricating a semiconductor device, a stack of alternating insulating layers and sacrificial layers are formed over a substrate. A staircase having a plurality of steps are formed in the stack, where each of the plurality of steps has a tread and a riser and further includes a respective pair of the insulating layer and the sacrificial layer over the insulating layer of the respective step. A dielectric layer is formed along the treads and risers of the plurality of steps. The dielectric layer is doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form word line layers that are arranged between the insulating layers. A plurality of word line contacts are formed to extend from the word line layers of the plurality of steps, and further extend through the dielectric layer.

Methods for forming a 3D memory device are provided. A method includes the following operations. A stack structure is formed in a staircase region and an array region. A dielectric material layer is formed over the array region and the staircase region. An etch mask layer is coated over the dielectric material layer. The etch mask layer, on a first surface away from the dielectric material layer, is planarized. The dielectric material layer and a remaining portion of the etch mask layer are etched to form a dielectric layer over the staircase region and the array region.

A nonvolatile memory device includes; a memory cell area including a common source plate, at least one cell structure under the common source plate, and a first metal pad under the at least one cell structure, and a peripheral circuit area on which the memory cell area is mounted, including a middle area , a first edge area, and a second metal pad on the first edge area. The memory cell area further includes a first contact extending from the common source plate and connected to the first metal pad. The peripheral circuit area further includes a second contact extending from a common source line switch and connected to the second metal pad. The first metal pad contacts with the second metal pad on the second metal pad.

Provided is a memory device, including: a substrate; a plurality of word lines, extending in a first direction, arranged in a second direction, disposed on the substrate; a dummy structure, adjacent to ends of the word lines, disposed on the substrate, wherein the dummy structure includes a main part that extends in the second direction; and a plurality of extension parts, extending in the first direction, connected to the main part, and interposed between the main part and the word lines.

A semiconductor device includes a lower stepped connection part at a first vertical level on a substrate, an upper stepped connection part at a second vertical level higher than the first vertical level on the substrate, a lower insulating block contacting each of the plurality of lower conductive pad parts at the first vertical level, an upper insulating block contacting each of the plurality of upper conductive pad parts at the second vertical level, an intermediate insulating film between the lower insulating block and the upper insulating block at a third vertical level between the first and second vertical levels, and a first plug structure extending into the lower stepped connection part, the intermediate insulating film, and the upper insulating block in the vertical direction, wherein a width of the first plug structure in the horizontal direction is greatest at the third vertical level.

Microelectronic devices include a stack structure having a vertically alternating sequence of insulative structures and conductive structures arranged in tiers. At least one stadium, of stadiums within the stack structure, comprise staircase(s) having steps provided by a group of the conductive structures. Step contacts extend to the steps of the staircase(s) of the at least one of the stadiums. Each conductive structure of the group of conductive structures has more than one of the step contacts in contact therewith at at least one of the steps of the staircase(s). Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.