A semiconductor device includes a first substrate, circuit devices disposed on the first substrate, a first interconnection structure electrically connected to the circuit devices, a second substrate disposed on an upper portion of the first interconnection structure, gate electrodes spaced apart from each other and stacked on the second substrate in a direction perpendicular to an upper surface of the second substrate, and channel structures penetrating the gate electrodes, extending perpendicularly to the second substrate, and including a channel layer. The semiconductor device also includes a ground interconnection structure connecting the first substrate and the second substrate, and including an upper via integrated with the second substrate and extending from a lower surface of the second substrate towards the first substrate.

A semiconductor device according to one embodiment includes a stacked body including first films and second films that are stacked alternatively one on another, the stacked body having a stair shape at end portions thereof; a thick film portion thicker than the second films within the stacked body and provided on an upper surface of a first step of the stair shape; a separating portion provided on a side face between the first step and a second step one-step above the first step, the separating portion separating the thick film portion from the side surface; a third film provided to cover the stacked body and the thick film portion; and an electrically conductive column portion penetrating through the third film to be in contact with the thick film portion.

A semiconductor device includes a plurality of semiconductor elements, each of the plurality of semiconductor elements including an active region disposed on a substrate, and a gate structure intersecting the active region and extending in a first direction that is parallel to an upper surface of the substrate; and at least one dummy element disposed between a pair of semiconductor elements adjacent to each other in a second direction, intersecting the first direction, among the plurality of semiconductor elements. The dummy element includes a dummy active region and at least one dummy gate structure intersecting the dummy active region and extending in the first direction. A length of the dummy active region in the second direction is less than a length of the active region included in each of the pair of semiconductor elements.

A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.

A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers, the stack structure divided into block structures separated from one another by slot structures, a staircase structure within the stack structure having steps comprising horizontal edges of the tiers, conductive contact structures in contact with the steps of the staircase structure, support pillar structures extending through the stack structure, and additional slot structures extending partially through the stack structure within one of the block structures, one of the additional slot structures extending between horizontally neighboring support pillar structures and closer to one of the horizontally neighboring support pillar structures than to an additional one of the horizontally neighboring support pillar structures. Related microelectronic devices, memory devices, and electronic systems are also described.

A method for manufacturing a semiconductor device may include: forming a plurality of stacked structures over a substrate, the substrate including one or more peripheral circuit regions and one or more cell regions, the stacked structures including first conductive lines and initial memory cells respectively disposed over the first conductive lines, each of the stacked structures extending in a first direction; forming a first insulating layer between the stacked structures; forming second conductive lines over the stacked structures and the first insulating layer, each of the second conductive lines extending in a second direction; forming memory cells by etching the initial memory cells exposed by the second conductive lines; forming a second insulating layer between the second conductive lines and between the memory cells; and removing the first conductive lines, the memory cells, and the second conductive lines in the peripheral circuit regions.

A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.

A three-dimensional memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, memory stack structures extending through the first alternating stack, a second alternating stack of second insulating layers and second electrically conductive layers located over the substrate and laterally spaced from the first alternating stack, a contact-level dielectric layer overlying the first alternating stack and the second alternating stack, a planar semiconductor material layer bonded to the contact-level dielectric layer and over an area of the second alternating stack, and field effect transistors located on the planar semiconductor material layer and electrically connected to the first electrically conductive layers.

A semiconductor memory device includes a stack structure comprising horizontal electrodes sequentially stacked on a substrate including a cell array region and an extension region and horizontal insulating layers between the horizontal electrodes. The semiconductor memory device may further include vertical structures that penetrate the stack structure, a first one of the vertical structures being on the cell array region and a second one of the vertical structures being on the extension region. Each of the vertical structures includes a channel layer, and a tunneling insulating layer, a charge storage layer and a blocking insulating layer which are sequentially stacked on a sidewall of the channel layer. The charge storage layer of the first vertical structure includes charge storage patterns spaced apart from each other in a direction perpendicular to a top surface of the substrate with the horizontal insulating layers interposed therebetween. The charge storage layer of the second vertical structure extends along sidewalls of the horizontal electrodes and sidewalls of the horizontal insulating layers.