A microelectronic device is disclosed, comprising: a stack structure comprising vertically alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, the stack structure having blocks separated from one another by filled slot structures; a source tier structure underlying the stack structure and comprising: a merged conductive structure adjacent a first discrete conductive structure in a first direction; and a second discrete conductive structure in the first direction that is spaced apart from the merged conductive by the first discrete conductive structure; a first support contact structure on the first discrete conductive structure; and a subsequent support contact structure on the merged conductive structure and adjacent the first support contact in the first direction, wherein one of the filled slot structures is vertically directly above at least a portion of the merged conductive structure.

A semiconductor device may include a first cell structure, a second cell structure, a pad structure, a circuit, and one or more openings. The pad structure may be disposed between the first cell structure and the second cell structure, and may be electrically coupled to the first and second cell structures. The pad structure may have a plurality of stepped structures. The circuit may be disposed under the pad structure. The one or more openings may pass through the pad structure, and may expose the circuit. The one or more openings may be disposed between the plurality of stepped structures.

In certain aspects, a three-dimensional (3D) memory device includes a memory stack including interleaved conductive layers and dielectric layers, a channel structure extending through the memory stack, and a through array contact (TAC) extending through the memory stack. Edges of the conductive layers along a sidewall of the TAC are recessed. The TAC includes a conductor layer and a spacer over the sidewall of the TAC.

A semiconductor structure is provided. The semiconductor structure includes a staircase structure including a first stair layer and a second stair layer on the first stair layer. The first stair layer comprises a first conductive film. The semiconductor structure includes a landing pad disposed on the first conductive film. The landing pad has a first pad sidewall facing toward the second stair layer, a first lateral gap distance between an upper portion of the first pad sidewall and the second stair layer is smaller than a second lateral gap distance between a lower portion of the first pad sidewall and the second stair layer.

A 3D memory device may include a logic device layer on a substrate and a memory device layer stacked on the logic device layer. The logic device layer may include logic devices disposed on the substrate. The memory device layer may include a word line stack disposed in an extension area, staircase patterns disposed in the word line stack, a dielectric layer stack in a peripheral area, and capacitors inlayed in the dielectric layer stack.

A semiconductor device includes a stacked structure including a first region in which conductive layers and the insulating layers are stacked alternately with each other, and a second region in which sacrificial layers and the insulating layers are stacked alternately with each other, a first slit structure located at a boundary between the first region and the second region and including a first through portion passing through the stacked structure and first protrusions extending from a sidewall of the first through portion, a second slit structure located at the boundary and including a second through portion passing through the stacked structure and second protrusions extending from a sidewall of the second through portion and coupled to the first protrusions, a circuit located under the stacked structure, and a contact plug passing through the second region of the stacked structure and electrically connected to the circuit.

Conductive structures include stair step structures positioned along a length of the conductive structure and at least one landing comprising at least one via extending through the conductive structure. The at least one landing is positioned between a first stair step structure of the stair step structures and a second stair step structure of the stair step structures. Devices may include such conductive structures. Systems may include a semiconductor device and stair step structures separated by at least one landing having at least one via formed in the at least one landing. Methods of forming conductive structures include forming at least one via through a landing positioned between stair step structures.

Systems, apparatuses, and methods may provide for technology for forming a pre-offset platform on top of a substrate. A memory block is formed, where the memory block includes a staircase area and a memory array area located adjacent the staircase area. The memory array area includes a plurality of memory pillars extending into the memory block. The staircase area has a first height, the memory array area has a second height, and a tier expansion height is defined as a difference between the second height and the first height. The pre-offset platform is located between the substrate and the staircase area of the memory block. The pre-offset platform is oriented and arranged to offset the tier expansion height so that an upper surface of the staircase area and an upper surface of the memory array area are located in a same plane.

Systems, apparatuses, and methods may provide for technology that arranges stair wells for memory devices. The memory device includes a memory array and a memory block coupled to the memory array. The memory block includes a first through array via area and a first staircase area coupled to a plurality of decks. The first staircase area includes a first stair well and a second stair well located contiguous to the first stair well.

Devices and methods for forming a device are disclosed. The method includes providing a substrate having a memory array region. Front end of line (FEOL) process is performed to form components of memory cell pairs. The FEOL process forms storage gates, access gates or word lines, source/drain regions, spacers, erase gates and source line isolation dielectrics. The memory cell pair shares a common source line (SL). A SL strap opening is provided. The source line strap opening is formed between adjacent memory cell pair. The source line strap opening does not overlap the storage gate of the memory cell.