A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The stack structure comprises a first block structure comprising stair step structures spaced from each other by crest regions, the stair step structures each comprising steps defined at horizontal edges of the tiers of the conductive structures and the insulative structures, and a second block structure horizontally neighboring the first block structure and comprising additional stair step structures spaced from one another by additional crest regions, the additional stair step structures horizontally offset from the stair step structures of the first block structure, and a slot structure extending though the stack structure and interposed between the first block structure and the second block structure. Related microelectronic devices, electronic systems, and methods are also described.

A microelectronic device comprises a stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The stack structure comprises a first block structure comprising stair step structures spaced from each other by crest regions, the stair step structures each comprising steps defined at horizontal edges of the tiers of the conductive structures and the insulative structures, and a second block structure horizontally neighboring the first block structure and comprising additional stair step structures spaced from one another by additional crest regions, the additional stair step structures horizontally offset from the stair step structures of the first block structure, and a slot structure extending though the stack structure and interposed between the first block structure and the second block structure. Related microelectronic devices, electronic systems, and methods are also described.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes levels of conductive materials interleaved with levels of dielectric materials; memory cell strings including respective pillars extending through the levels of conductive materials and the levels of dielectric materials; a first dielectric structure formed in a first slit through the levels of conductive materials and the levels of dielectric materials; a second dielectric structure formed in a second slit through the levels of conductive materials and the levels of dielectric materials; the first dielectric structure and the second dielectric structure separating the levels of conductive materials, the levels of dielectric materials, and the pillars into separate portions, and the first and second dielectric structures including different widths.

A semiconductor device including a substrate including first, second, and third regions; a peripheral circuit structure on the substrate and including a peripheral circuit and wiring layers connected to the peripheral circuit; a common source plate on the peripheral circuit structure and extending in a horizontal direction; gate electrodes on the common source plate on the first and second regions, spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, the gate electrodes having a stair shape on the second region; a channel structure extending in the first direction through the gate electrodes on the first region; a first conductive through-via penetrating the common source plate on the third region and electrically connected to the wiring layers; and a dummy insulating pillar adjacent to the first conductive through-via on the third region and connected to an upper surface of the common source plate.

Microelectronic devices include a tiered stack having vertically alternating insulative and conductive structures. A first series of stadiums is defined in the tiered stack within a first block of a dual-block structure. A second series of stadiums is defined in the tiered stack within a second block of the dual-block structure. The first and second series of stadiums are substantially symmetrically structured about a trench at a center of the dual-block structure. The trench extends a width of the first and second series of stadiums. The stadiums of the first and second series of stadiums have opposing staircase structures comprising steps at ends of the conductive structures of the tiered stack. Conductive source/drain contact structures are in the stack and extend substantially vertically from a source/drain region at a floor of the trench. Additional microelectronic devices are also disclosed, as are methods of fabrication and electronic systems.

Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.

Embodiments of a three-dimensional (3D) memory device and fabrication methods thereof are disclosed. In an example, a 3D memory device includes a memory stack having a plurality of stairs. Each stair may include interleaved one or more conductor layers and one or more dielectric layers. Each of the stairs includes one of the conductor layers on a top surface of the stair, the one of the conductor layers having (i) a bottom portion in contact with one of the dielectric layers, and (ii) a top portion exposed by the memory stack and in contact with the bottom portion. A lateral dimension of the top portion may be less than a lateral dimension of the bottom portion. An end of the top portion that may be facing away from the memory stack laterally exceeds the bottom portion by a distance.

A semiconductor memory device includes: a semiconductor substrate including a first region and a second region; a memory cell array over the first region of the semiconductor substrate; a dummy stack structure over the second region of the semiconductor substrate; a chip guard structure penetrating the dummy stack structure; and a void-containing structure penetrating the dummy stack structure.

A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and an array of memory opening fill structures extending through the alternating stack, an array of drain-select-level assemblies overlying the alternating stack and having a same two-dimensional periodicity as the array of memory opening fill structures, a first strip electrode portion laterally surrounding a first set of multiple rows of drain-select-level assemblies within the array of drain-select-level assemblies, and a drain-select-level isolation strip including an isolation dielectric that contacts the first strip electrode portion and laterally spaced from the drain-select-level assemblies and extending between the first strip electrode portion and a second strip electrode portion.