The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers that are alternately stacked, a channel plug at least partially passing through the stack structure on a cell region, and a plurality of support structures at least partially passing through the stack structure on a contact region.

A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and extending by different lengths in a second direction on the second region to have pad regions in which upper surfaces thereof are exposed, channel structures penetrating the gate electrodes, extending in the first direction, and respectively including a channel layer, on the first region, contact plugs penetrating the pad regions of the gate electrodes and extending in the first direction, and contact insulating layers surrounding the contact plugs. The gate electrodes have side surfaces protruding further toward the contact plugs in the pad regions than ones of the gate electrodes therebelow.

A vertical memory device may include a first conductive line structure and an address decoder. The first conductive line structure may be on a substrate. The first conductive line structure may include conductive lines and insulation layers alternately and repeatedly stacked in a direction perpendicular to the substrate. The address decoder may be connected to a first end of each of conductive lines included in the first conductive line structure. The address decoder may apply electrical signal to the conductive lines. In each of the conductive lines, a first portion adjacent to the first end and a second portion adjacent to a second end may have different shapes. A first resistance in the first portion may be lower than a second resistance in the second portion. RC delay of the conductive lines may be reduced.

A semiconductor device includes a first substrate, circuit elements, lower interconnection lines, a second substrate, gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction and forming first and second stack structures, channel structures penetrating through the gate electrodes, and first and second contact plugs penetrating through the first and second stack structures, respectively, and connected to the gate electrodes. The first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the first contact plugs, respectively. The second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, and are connected to the second contact plugs, respectively. The first and second pad areas are offset in relation to each other so as not to overlap each other in the first direction.

A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.

A semiconductor device includes a peripheral circuit structure including a lower substrate, a plurality of circuits formed on the lower substrate, and a plurality of wiring layers connected to the plurality of circuits, an upper substrate covering the peripheral circuit structure and including a through opening, a memory stack structure including a plurality of gate lines, a memory cell contact passing through at least one of the plurality of gate lines to contact one gate line from among the plurality of gate lines, the memory cell contact extending to the peripheral circuit structure through the through opening and being configured to be electrically connected to a first wiring layer from among the plurality of wiring layers, and a plurality of dummy channel structures passing through at least one of the plurality of gate lines to extend to the peripheral circuit structure through the through opening.

According to one embodiment, a source layer includes a semiconductor layer including an impurity. A stacked body includes a plurality of electrode layers stacked with an insulator interposed. A gate layer is provided between the source layer and the stacked body. The gate layer is thicker than a thickness of one layer of the electrode layers. A semiconductor body extends in a stacking direction of the stacked body through the stacked body and the gate layer. The semiconductor body further extends in the semiconductor layer where a side wall portion of the semiconductor body contacts the semiconductor layer. The semiconductor body does not contact the electrode layers and the gate layer.

A three-dimensional semiconductor memory device may include a peripheral circuit structure including transistors on a first substrate, and a cell array structure on the peripheral circuit structure, the cell array structure including: a first stack structure block comprising first stack structures arranged side by side in a first direction on a second substrate, a second stack structure block comprising second stack structures arranged side by side in the first direction on the second substrate, a separation structure disposed on the second substrate between the first stack structure block and the second stack structure block and comprising first mold layers and second mold layers, and a contact plug penetrating the separation structure. The cell array structure may include a first metal pad and the peripheral circuit structure may include a second metal pad. The first metal pad may be in contact with the second metal pad.

A semiconductor device includes a peripheral circuit region including a first substrate and circuit elements on the first substrate; and a memory cell region including a second substrate on an upper portion of the first substrate, gate electrodes spaced apart from each other and vertically stacked on the second substrate, channel structures extending vertically through the gate electrodes to the second substrate, first separation regions penetrating through the gate electrodes between the channel structures and extending in one direction, and a second separation region extending vertically to penetrate through the second substrate from above and having a bent portion due to a change in width.

Semiconductor devices laterally surrounded by at least one dielectric material portion are formed over a substrate. At least one edge seal ring structure is formed around the semiconductor devices and the at least one dielectric material portion. One or more of the at least one edge seal ring structure has a horizontal cross-sectional profile that includes laterally-extending regions that extend laterally with a uniform width between an inner sidewall and an outer sidewall, and notch regions connecting neighboring pairs of the laterally-extending regions and having a greater width than the uniform width. Cavities in the laterally-extending regions are connected to cavities in the notch regions to allow outgassing from the material of the at least one edge seal ring structure.