An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.

A semiconductor device constituting a non-volatile memory includes a semiconductor portion of a first conductivity type, a first well of a second conductivity type, a second well of the second conductivity type, an insulating film, and a conductive layer. The first well includes a trench extending from the surface of the semiconductor portion to an inside of the first well. The insulating film extends on a surface inside the trench. A conductive portion formed continuous with the conductive layer is disposed on the insulating film inside the trench.

The present application discloses a semiconductor device with an oxidized intervention layer and a method for fabricating the semiconductor device. The semiconductor device includes a substrate, a memory unit including a memory unit conductive layer positioned above the substrate and a lateral oxidized intervention layer positioned below the memory unit conductive layer, and a control unit positioned in the substrate and below the lateral oxidized intervention layer. The lateral oxidized intervention layer includes a sidewall portion and a center portion, and the sidewall portion has a greater concentration of oxygen than the center portion.

The semiconductor device includes a substrate, a stack structure including gate patterns and interlayer insulating films that are alternately stacked on the substrate, an insulating pillar extending in a thickness direction of the substrate within the stack structure, a polycrystalline metal oxide film extending along a sidewall of the insulating pillar between the insulating pillar and the stack structure, a liner film having a transition metal between the insulating pillar and the polycrystalline metal oxide film, and a tunnel insulating film, a charge storage film, and a blocking insulating film which are disposed in order between the polycrystalline metal oxide film and the gate patterns.

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

A memory structure including a first select transistor, a first floating gate transistor, a second select transistor, a second floating gate transistor, and a seventh doped region is provided. The first select transistor includes a select gate, a first doped region, and a second doped region. The first floating gate transistor includes a floating gate, the second doped region, and a third doped region. The second select transistor includes the select gate, a fourth doped region, and a fifth doped region. The second floating gate transistor includes the floating gate, the fifth doped region, and a sixth doped region. A gate width of the floating gate in the second floating gate transistor is greater than a gate width of the floating gate in the first floating gate transistor. The floating gate covers at least a portion of the seventh doped region.

A nonvolatile memory device includes a peripheral circuit including a first active region and a memory block including a second active region on the peripheral circuit. The memory block includes a vertical structure including pairs of a first insulating layer and a first conductive layer, a second insulating layer on the vertical structure, a second conductive layer and a third conductive layer spaced apart from each other on the second insulating layer, first vertical channels and second vertical channels. The second conductive layer and the third conductive layer are connected with a first through via penetrating the vertical structure, the second active region, and a region of the second insulating layer that is exposed between the second conductive layer and the third conductive layer.

A three-dimensional memory device includes alternating stacks of insulating layers and electrically conductive layers located over a semiconductor material layer, and memory stack structures extending through one of the alternating stacks. Laterally-undulating backside trenches are present between alternating stacks, and include a laterally alternating sequence of straight trench segments and bulging trench segments. Cavity-containing dielectric fill structures and contact via structures are present in the laterally-undulating backside trenches. The contact via structures are located within the bulging trench segments. The contact via structures are self-aligned to sidewalls of the alternating stacks. Additional contact via structures may vertically extend through a dielectric alternating stack of a subset of the insulating layers and dielectric spacer layers laterally adjoining one of the alternating stacks.

A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

An operating method of an EEPROM cell is provided. The EEPROM cell comprises a transistor structure disposed on a semiconductor substrate and the transistor structure comprises a first electric-conduction gate. The-same-type ions are implanted into the semiconductor substrate between an interface of its source, drain and the first electric-conduction gate, or into the ion doped regions of the source and the drain, so as to increase ion concentrations in the implanted regions and reduce voltage difference in writing and erasing operations. The operating method of the EEPROM cell provides an operating condition that the drain or the source is set as floating during operations, to achieve the objective of rapid writing and erasing of a large number of memory cells. The proposed operating method is also applicable to the EEPROM cell having a floating gate structure in addition to a single gate transistor structure.