A random bit cell incudes a random bit cell. The random bit cell includes a volatile memory unit, a first non-volatile memory unit, a second non-volatile memory unit, a first select transistor, and a second select transistor. The first non-volatile memory unit is coupled to a first data terminal of the volatile memory unit, and the second non-volatile memory unit is coupled to a second data terminal of the volatile memory unit. The first select transistor has a first terminal coupled to the first data terminal of the volatile memory unit, a second terminal coupled to a first bit line, and a control terminal coupled to a word line. The second select transistor has a first terminal coupled to the second data terminal of the volatile memory unit, a second terminal coupled to a second bit line, and a control terminal coupled to a word line.

A non-volatile memory cell includes a floating-gate transistor, a select transistor, and a coupling structure. The floating-gate transistor is deposited in a P-well and includes a gate terminal coupled to a floating gate which is a first polysilicon layer, a drain terminal coupled to a bit line, and a source terminal coupled to a first node. The select transistor is deposited in the P-well and includes a gate terminal coupled to a select gate which is coupled to a word line, a drain terminal coupled to the first node, and a source terminal coupled to the source line. The floating-gate transistor and the select transistor are N-type transistors. The coupling structure is formed by extending the first polysilicon layer to overlap a control gate, in which the control gate is a P-type doped region in an N-well and the control gate is coupled to a control line.

A level shifting circuit generates a pulse signal, when both of the logic levels of two complementary input signals of a level shifter has changed while both of the logic levels of two output signals of the level shifter present at low logic level, to pull up either one of the output signals of the level shifter to a second high logic level. Once the logic level of both output signals at the first output node and the second output node present complementary, the level shifting circuit stops pulling up the output signal.

A non-volatile memory and fabrication method thereof are disclosed. The non-volatile memory includes at least one 2T memory cell. Each 2T memory cell includes a semiconductor substrate, a first stacked gate and a second stacked gate formed on the semiconductor substrate, and a drain region, a common source/drain region and a source region formed in the semiconductor substrate. The source region and the common source/drain region are both N-type doped, and the drain region includes an N-type doped region and a heavily P-type doped region formed in the N-type doped region. The 2T memory cell is capable of preventing erroneous data determination caused by over erase and has both a low programming current and a high reading current, which improves the performance of the non-volatile memory.

A non-volatile memory and fabrication method thereof are disclosed. The non-volatile memory includes at least one 2T memory cell. Each 2T memory cell includes a semiconductor substrate, a first stacked gate and a second stacked gate formed on the semiconductor substrate, and a drain region, a common source/drain region and a source region formed in the semiconductor substrate. The source region and the common source/drain region are both N-type doped, and the drain region includes an N-type doped region and a heavily P-type doped region formed in the N-type doped region. The 2T memory cell is capable of preventing erroneous data determination caused by over erase and has both a low programming current and a high reading current, which improves the performance of the non-volatile memory.

Representative methods of manufacturing memory devices include forming a transistor with a gate disposed over a workpiece, and forming an erase gate with a tip portion extending towards the workpiece. The transistor includes a source region and a drain region disposed in the workpiece proximate the gate. The erase gate is coupled to the gate of the transistor.

An electrical isolation device including a support with thickness E including two faces facing one another, referred to, respectively, as the two faces having a length L, a width l; on each face of the support, a plurality of voltage dividers is positioned extending over the length, each voltage divider including electrical components that are connected in series and arranged according to a first and a second stage, each first stage including a row of even components and a row of odd components, the rows being parallel, and adjacent, and the second stage corresponding to a linear arrangement of components.

Devices and methods of forming a device are disclosed. The device includes a substrate defined with at least a device region. A multi-gate transistor disposed in the device region which includes first and second gates both having first and second gate sidewalls. The multi-gate transistor also includes first source/drain (S/D) regions disposed adjacent to the first gate sidewall of the first and second gate, a common second S/D region disposed adjacent to the second gate sidewall of the first and second gate. A negative capacitance element is disposed within the second gate to reduce total overlap capacitance of the transistor. An interlevel dielectric (ILD) layer is disposed over the substrate and covering the transistor. First and second contacts are disposed in the ILD layer which are coupled to the first and second S/D regions respectively.

Some embodiments include apparatuses and methods of forming such apparatuses. One of the apparatus includes first memory cells located in different levels in a first portion of the apparatus, second memory cells located in different levels in a second portion of the apparatus, a switch located in a third portion of the apparatus between the first and second portions, first and second control gates to access the first and second memory cells, an additional control gate located between the first and second control gates to control the switch, a first conductive structure having a thickness and extending perpendicular to the levels in the first portion of the apparatus, a first dielectric structure between the first conductive structure and charge-storage portions of the first memory cells, a second dielectric structure having a second thickness between the second conductive structure and a sidewall of the additional control gate, the second thickness being greater than the first thickness.

A non-volatile memory cell and array structure is disclosed situated within a high voltage region of an integrated circuit. The cell utilizes capacitive coupling based on an overlap between a gate and a drift region to impart a programming voltage. Programming is effectuated using a drain extension which can act to inject hot electrons. The cell can be operated as a one-time programmable (OTP) or multiple-time programmable (MTP) device. The fabrication of the cell relies on processing steps associated with high voltage devices, thus avoiding the need for additional masks, manufacturing steps, etc.