An integrated circuit (IC) structure includes a semiconductor fin having a first longitudinal extent and a second longitudinal extent. The semiconductor fin has an upper fin portion having a uniform lateral dimension in the first longitudinal extent and the second longitudinal extent, a first subfin portion under the upper fin portion in the first longitudinal extent having a first lateral dimension, and a second subfin portion under the upper fin portion in the second longitudinal extent having a second lateral dimension different than the first lateral dimension. The second subfin may be used in a drain extension region of a laterally-diffused metal-oxide semiconductor (LDMOS) device. The second subfin reduces subfin current and improves HCI reliability, regardless of the type of LDMOS device.

Memory devices are disclosed. In an embodiment of the disclosed technology, a memory device may include a substrate including an active region, and a first floating gate, a second floating gate, a third floating gate and a fourth floating gate formed on the substrate, arranged to partially overlap with the active region. The first floating gate and the third floating gate are arranged in a first direction at one side of the active region and asymmetrical about a center of the active region, and the second floating gate and the fourth floating gate are arranged in the first direction at another side of the active region and asymmetrical about the center of the active region.

A multi-time programming non-volatile memory includes a select transistor, a floating gate transistor, a switch transistor, a capacitor and an erase gate element. The select transistor is connected with a select line and a source line. The floating gate transistor includes a floating gate. The floating gate transistor is connected with the select transistor. The switch transistor is connected with a word line, the floating gate transistor and a bit line. A first terminal of the capacitor is connected with the floating gate. A second terminal of the capacitor is connected with a control line. The erase gate element includes the floating gate, a gate oxide layer and a p-type region. The erase gate element is connected with an erase line. The floating gate of the erase gate element at least includes an n-type floating gate part.

A memory structure and its fabrication method are provided in the present disclosure. The method includes providing a substrate, forming a plurality of discrete memory gate structures on the substrate where an isolation trench is between adjacent memory gate structures and a memory gate structure includes a floating gate layer and a control gate layer, forming an isolation layer in the isolation trench where a top surface of the isolation layer is lower than a top surface of the control gate layer and higher than a bottom surface of the control gate layer, forming an opening on an exposed sidewall of the control gate layer where a bottom of the opening is lower than or coplanar with the top surface of the isolation layer, and forming an initial metal silicide layer on an exposed surface of the control gate layer and the top surface of the isolation layer.

An erasable programmable single-poly non-volatile memory cell and an associated array structure are provided. In the memory cell of the array structure, the assist gate region is composed at least two plate capacitors. Especially, the assist gate region at least contains a poly/poly plate capacitor and a metal/poly plate capacitor. The structures and the fabricating processes of the plate capacitors are simple. In addition, the uses of the plate capacitors can effectively reduce the size of the memory cell.

A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device comprises providing a first substrate including a buffer layer and a base substrate, forming a stacked mold structure including a plurality of unit laminates on the buffer layer, each of the unit laminates including a first sacrificial layer, a first silicon layer, a second sacrificial layer, and a second silicon layer sequentially stacked in a vertical direction and replacing the stacked mold structure with a stacked memory structure through a replacement process, wherein the stacked memory structure includes a metal pattern which replaces the first sacrificial layer and the second sacrificial layer, and an insulating pattern which replaces the second silicon layer, the buffer layer includes silicon-germanium, and a germanium concentration of the buffer layer varies depending on the germanium concentration of the first sacrificial layer and the germanium concentration of the second sacrificial layer.

A method for manufacturing a semiconductor device is provided. The method for manufacturing a semiconductor device comprises providing a first substrate including a buffer layer and a base substrate, forming a stacked mold structure including a plurality of unit laminates on the buffer layer, each of the unit laminates including a first sacrificial layer, a first silicon layer, a second sacrificial layer, and a second silicon layer sequentially stacked in a vertical direction and replacing the stacked mold structure with a stacked memory structure through a replacement process, wherein the stacked memory structure includes a metal pattern which replaces the first sacrificial layer and the second sacrificial layer, and an insulating pattern which replaces the second silicon layer, the buffer layer includes silicon-germanium, and a germanium concentration of the buffer layer varies depending on the germanium concentration of the first sacrificial layer and the germanium concentration of the second sacrificial layer.

A memory cell including a substrate having a first doped region and a second doped region spaced apart from each other and defining a channel region therebetween, a floating gate including a first end over the channel region and a second end over the first doped region, a control gate including a first portion arranged laterally adjacent to the second end of the floating gate and a second portion arranged over and overlapping the second end of the floating gate, a word line overlapping the channel region, the first end of the floating gate, and the second portion the control gate, a first insulation member separating the floating gate, the control gate and the word line from the substrate; a second insulation member separating the floating gate from the control gate, and a third insulation member separating the floating gate and the control gate from the word line.

A memory cell including a substrate having a first doped region and a second doped region spaced apart from each other and defining a channel region therebetween, a floating gate including a first end over the channel region and a second end over the first doped region, a control gate including a first portion arranged laterally adjacent to the second end of the floating gate and a second portion arranged over and overlapping the second end of the floating gate, a word line overlapping the channel region, the first end of the floating gate, and the second portion the control gate, a first insulation member separating the floating gate, the control gate and the word line from the substrate; a second insulation member separating the floating gate from the control gate, and a third insulation member separating the floating gate and the control gate from the word line.

For erasing four-terminal semiconductor Non-Volatile Memory (NVM) devices, we apply a high positive voltage bias to the control gate with source, substrate and drain electrodes tied to the ground voltage for moving out stored charges in the charge storage material to the control gate. For improving erasing efficiency and NVM device endurance life by lowering applied voltage biases and reducing the applied voltage time durations, we engineer the lateral impurity profile of the control gate near dielectric interface such that tunneling occurs on the small lateral region of the control gate near the dielectric interface. We also apply the non-uniform thickness of coupling dielectric between the control gate and the storage material for the NVM device such that the tunneling for the erase operation occurs within the small thin dielectric areas, where the electrical field in thin dielectric is the strongest for tunneling erase operation.