A neuromorphic device having a synapse array is provided. The synapse array of the neuromorphic device may include an input neuron; an output neuron; and a synapse. The synapse may include a plurality of ferroelectric field effect transistors electrically connected to each other in parallel.

A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.

A semiconductor device with less variations in transistor characteristics is provided.

A first insulator is deposited; an island-shaped stacked body in which a first oxide, a second oxide, and a first conductor are stacked in this order is formed over the first insulator; a second insulator is formed over the first insulator and the stacked body; an opening portion for exposing the stacked body is formed in the second insulator; a top surface of the second oxide is exposed by removing a region of the first conductor exposed in the opening portion, a second conductor and a third conductor are formed over the second oxide, and then cleaning treatment is performed; a first oxide film is deposited in contact with a side surface of the first oxide and top and side surfaces of the second oxide that are exposed in the opening portion; oxygen addition treatment is performed on a vicinity of an interface between the second oxide and the first oxide film through the first oxide film and then heat treatment is performed; and a first insulating film and a first conductive film are deposited over the first oxide film, and then parts of the first conductive film, the first insulating film, the first oxide film, and the second insulator are removed by chemical polishing treatment to expose the second insulator and form a fourth conductor, a third insulator, and a third oxide in the opening portion provided in the second insulator.

A semiconductor device with a large storage capacity per unit area can be provided. A memory cell including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor includes a stack including a first conductor, a first insulator over the first conductor, a second conductor over the first insulator, a second insulator over the second conductor, and a third conductor over the second insulator; a first oxide arranged in a ring-like shape on a side surface of an opening portion of the second conductor; a fourth conductor arranged in a ring-like shape in contact with an inner wall of the first oxide; a cylindrical third insulator arranged to penetrate the stack, the first oxide, and the fourth conductor; and a second oxide arranged in contact with an inner wall of the third insulator.

A semiconductor device with small variations in transistor characteristics is provided. The semiconductor device includes an oxide; a first conductor and a second conductor provided apart from each other over the oxide; an insulator in a region between the first conductor and the second conductor over the oxide; and a conductor over the insulator. A side surface of the oxide, a top surface of the first conductor, a side surface of the first conductor, a top surface of the second conductor, and a side surface of the second conductor include regions in contact with a nitride containing silicon.

A semiconductor device capable of retaining a signal sensed by a sensor element is provided. The semiconductor device includes a sensor element, a first transistor, a second transistor, and a third transistor. One electrode of the sensor element is electrically connected to a first gate. The first gate is electrically connected to one of a source and a drain of the third transistor. One of a source and a drain of the first transistor is electrically connected to a gate of the second transistor. A semiconductor layer includes a metal oxide.

A memory device is disclosed. The memory device includes: a first memory cell, including: a first transistor; a second transistor; and a first capacitor; a second memory cell, including: a third transistor; a fourth transistor; and a second capacitor; a third memory cell, including: a fifth transistor; a sixth transistor; and a third capacitor; and a fourth memory cell, including: a seventh transistor; an eighth transistor; and a fourth capacitor; wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor. An associated manufacturing method is also disclosed.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

A semiconductor device that is miniaturized and highly integrated is provided. One embodiment of the present invention is a semiconductor device including a first insulator, a second insulator, a first conductor, a second conductor, and a semiconductor layer; the first insulator includes an opening exposing the semiconductor layer; the first conductor is provided in contact with the semiconductor layer at a bottom of the opening; the second insulator is provided in contact with a top surface of the first conductor and a side surface in the opening; the second conductor is provided in contact with the top surface of the first conductor and in the opening with the second insulator therebetween; and the second insulator has a barrier property against oxygen.

A novel semiconductor device is provided. The semiconductor device includes a driver circuit including a plurality of transistors using a silicon substrate for channels, and a first transistor layer and a second transistor layer including a plurality of transistors using a metal oxide for channels. The first transistor layer and the second transistor layer are provided over the silicon substrate layer. The first transistor layer includes a first memory cell including a first transistor and a first capacitor. The first transistor is electrically connected to a first local bit line. The second transistor layer includes a second transistor whose gate is electrically connected to the first local bit line and a first correction circuit electrically connected to the second transistor. The first correction circuit is electrically connected to a first global bit line. The first correction circuit has a function of holding a voltage corresponding to a threshold voltage of the second transistor in the gate of the second transistor.