A stack with excellent electrical characteristics and reliability is provided. The stack includes an insulator, a conductor, and a first oxide between the insulator and the conductor; the first oxide includes a first c-axis-aligned crystal region; and a c-axis of the first crystal region is substantially perpendicular to a plane of the first oxide on the insulator side. Alternatively, the stack includes an insulator, a conductor, a first oxide between the insulator and the conductor, and a second oxide facing the first oxide with the insulator therebetween; the first oxide includes a first c-axis-aligned crystal region; a c-axis of the first crystal region is substantially perpendicular to a plane of the first oxide on the insulator side; the second oxide includes a second c-axis-aligned crystal region; and a c-axis of the second crystal region is substantially perpendicular to a plane of the second oxide on the insulator side.

A chip package comprises an interposer; an FPGA IC chip over the interposer, wherein the FPGA IC chip comprises a programmable logic block configured to perform a logic operation on its inputs, wherein the programmable logic block comprises a look-up table configured to be provided with multiple resulting values of the logic operation on multiple combinations of the inputs of the programmable logic block respectively, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values into its output, and multiple non-volatile memory cells configured to save the resulting values respectively; multiple first metal bumps between the interposer and the FPGA IC chip; and an underfill between the interposer and the FPGA IC chip, wherein the underfill encloses the first metal bumps.

It is an object to provide a memory device whose power consumption can be suppressed and a semiconductor device including the memory device. As a switching element for holding electric charge accumulated in a transistor which functions as a memory element, a transistor including an oxide semiconductor film as an active layer is provided for each memory cell in the memory device. The transistor which is used as a memory element has a first gate electrode, a second gate electrode, a semiconductor film located between the first gate electrode and the second gate electrode, a first insulating film located between the first gate electrode and the semiconductor film, a second insulating film located between the second gate electrode and the semiconductor film, and a source electrode and a drain electrode in contact with the semiconductor film.

A memory device is disclosed. The memory device includes: a first memory cell, including: a first transistor; a second transistor; and a first capacitor; a second memory cell, including: a third transistor; a fourth transistor; and a second capacitor; a third memory cell, including: a fifth transistor; a sixth transistor; and a third capacitor; and a fourth memory cell, including: a seventh transistor; an eighth transistor; and a fourth capacitor; wherein an electrode of the first capacitor, an electrode of the second capacitor, an electrode of the third capacitor, and an electrode of the fourth capacitor are electrically connected to a conductor. An associated manufacturing method is also disclosed.

A novel metal oxide is provided. One embodiment of the present invention is a crystalline metal oxide. The metal oxide includes a first layer and a second layer; the first layer has a wider bandgap than the second layer; the first layer and the second layer form a crystal lattice; and in the case where a carrier is excited in the metal oxide, the carrier is transferred through the second layer. Furthermore, the first layer contains an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn, and the second layer contains In.

A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

A semiconductor device including: a first insulator in which an opening is formed; a first conductor positioned in the opening; a first oxide over the first insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide and the first conductor; a third conductor over the fourth oxide; a fifth oxide over the second oxide; a second insulator over the fifth oxide; and a fourth conductor positioned over the second insulator and overlapping with the fifth oxide. The fifth oxide is in contact with each of a side surface of the third oxide and a side surface of the fourth oxide. The conductivity of the third oxide is higher than the conductivity of the second oxide. The second conductor is in contact with the top surface of the first conductor.

A semiconductor device with a novel structure is provided. The semiconductor device includes a mixer circuit including a digital-analog converter circuit, a control circuit for controlling the digital-analog converter circuit, a power source control switch, and a plurality of Gilbert circuits. The plurality of Gilbert circuits each include an analog potential holding circuit for holding an analog potential output from the digital-analog converter circuit. The control circuit has a function of outputting a signal for controlling the analog potential holding circuit and the digital-analog converter circuit. The power source control switch has a function of stopping supply of a power source voltage to the control circuit in a period during which the analog potential held in the analog potential holding circuit is not updated. The analog potential holding circuit includes a first transistor. The first transistor includes a semiconductor layer including an oxide semiconductor in a channel formation region.

The semiconductor device includes a first memory cell, and a second memory cell thereover. The first memory cell includes first and second transistors, and a first capacitor. The second memory cell includes third and fourth transistors, and a second capacitor. A gate of the first transistor is electrically connected to one of a source and a drain of the second transistor and the first capacitor. A gate of the third transistor is electrically connected to one of a source and a drain of the fourth transistor and the second capacitor. One of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the third transistor. The second and fourth transistors include an oxide semiconductor. A channel length direction of the first and third transistors is substantially perpendicular to a channel length direction of the second and fourth transistors.

A transistor with a high on-state current and a semiconductor device with high productivity are provided. A first insulator; a second insulator over the first insulator; a third insulator and a first conductor over the second insulator; a fourth insulator over the third insulator and the first conductor; a fifth insulator over the fourth insulator; a first oxide over the fifth insulator; a second oxide over the first oxide; a third oxide and a fourth oxide over the second oxide; a second conductor over the third oxide; a third conductor over the fourth oxide; a sixth insulator over the second conductor; a seventh insulator over the third conductor; an eighth insulator over the fifth insulator to the seventh insulator; a fifth oxide over the second oxide and positioned between the second conductor and the third conductor; a ninth insulator over the fifth oxide; and a fourth conductor over the ninth insulator are included. Hydrogen concentration of the first conductor is lower than hydrogen concentration of the fourth conductor.