Some implementations described herein provide a semiconductor structure. The semiconductor structure includes a first terminal coupled to a substrate of the semiconductor structure, with the first terminal including a first portion of a tunneling layer formed on the substrate, and a first gate formed on the first portion of the tunneling layer. The semiconductor structure includes a second terminal coupled to the substrate and adjacent to the first terminal, with the second terminal including a second portion of the tunneling layer formed on the substrate, a second gate formed on the second portion of the tunneling layer, and a dielectric structure formed on a top surface and side surfaces of the second gate. The semiconductor structure includes a third terminal coupled to an insulating structure and adjacent to the second terminal, with the third terminal including, a third gate formed on the insulating structure.

A novel deposition method of a metal oxide is provided. The deposition method includes a first step of supplying a first precursor to a chamber; a second step of supplying a second precursor to the chamber; a third step of supplying a third precursor to the chamber; and a fourth step of introducing an oxidizer into the chamber after the first step, the second step, and the third step. The first to third precursors are different kinds of precursors, and a substrate placed in the chamber in the first to fourth steps is heated to a temperature higher than or equal to 300° C. and lower than or equal to decomposition temperatures of the first to third precursors.

Power consumption is reduced. A semiconductor device includes a sensor circuit including a sensor element, a power management unit, and an arithmetic processing circuit. The power management unit has a function of controlling power supply to the arithmetic processing circuit. The arithmetic processing circuit includes a first circuit including a first storage circuit and a second circuit including a second storage circuit. The first circuit has a function of retaining first data in the first storage circuit during a period where electric power is supplied to the arithmetic processing circuit. The second circuit has a function of reading out the first data retained in the first storage circuit and writing the first data to the second storage circuit during a period where electric power is supplied to the arithmetic processing circuit, and a function of retaining the first data in the second storage circuit during a period where power supply to the arithmetic processing circuit is stopped. The sensor circuit has a function of judging a sensed signal of the sensor element and supplying second data to the power management unit in accordance with the judgment result. The power management unit has a function of restarting or stopping power supply to the arithmetic processing circuit in accordance with the second data.

A semiconductor device having a large on-state current and high reliability is provided. The semiconductor device includes a first insulator, a first oxide over the first insulator, a second oxide over the first oxide, a third oxide and a fourth oxide over the second oxide, a first conductor over the third oxide, a second conductor over the fourth oxide, a fifth oxide over the second oxide, a second insulator over the fifth oxide, and a third conductor over the second insulator. The fifth oxide is in contact with a top surface of the second oxide, a side surface of the first conductor, a side surface of the second conductor, a side surface of the third oxide, and a side surface of the fourth oxide. The second oxide contains In, an element M, and Zn. The first oxide and the fifth oxide each contain at least one of constituent elements included in the second oxide. The third oxide and the fourth oxide each contain the element M. The third oxide and the fourth oxide include a region where the concentration of the element M is higher than that in the second oxide.

A semiconductor device with a novel structure is provided. The semiconductor device includes a plurality of memory circuits, a switching circuit, a first arithmetic circuit, and a second arithmetic circuit. The plurality of memory circuits each have a function of retaining weight data. The switching circuit has a function of switching electrical continuity and discontinuity between any one of the memory circuits and the first arithmetic circuit. The first arithmetic circuit outputs a first output signal based on product-sum operation processing of input data and the weight data selected by the switching circuit to the second arithmetic circuit. A layer including the plurality of memory circuits is provided to be stacked over a layer including the switching circuit, the first arithmetic circuit, and the second arithmetic circuit.

In an embodiment a non-volatile memory cell includes a substrate, a first body in the substrate, a second body in the substrate, a first storage transistor having a first conduction region and a second conduction region in the first body, the first and second conduction regions delimiting a first channel region in the first body, a first control gate region in the second body, an insulating region overlying the substrate, a single floating gate region extending on the substrate and embedded in the insulating region, the single floating gate region having a first portion on the first body and a second portion on the second body, the first portion and second portion being connected and electrically coupled, a first selection via extending through the insulating region and electrically coupling the first conduction region with a first conduction node, a second selection via extending through the insulating region and electrically coupling the second conduction region with a second conduction node and a first control via extending though the insulating region and electrically coupling the first control gate region with a first control node.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes an oxide, a first conductor and a second conductor over the oxide, a first insulator over the first conductor, a second insulator over the second conductor, a third insulator over the first insulator and the second insulator, a fourth insulator over the third insulator, a fifth insulator that is over the oxide and is located between the first conductor and the second conductor; a sixth insulator over the fifth insulator; a seventh insulator over the sixth insulator, and a third conductor over the seventh insulator. The third conductor includes a region overlapping with the oxide, the fifth insulator has a region that is in contact with each of the oxide, the first conductor, the second conductor, and the first to fourth insulators, and the sixth insulator contains hydrogen, nitrogen, oxygen, and silicon.

A method for manufacturing a semiconductor device with a high yield is provided. In a semiconductor device including an oxide semiconductor over a substrate, when an insulator in contact with the oxide semiconductor, such as a gate insulator or an interlayer film, is deposited, the insulator can be deposited without diffusion of hydrogen into the oxide semiconductor by setting a constant derived from deposition conditions within a given range. Specifically, setting values of deposition power, the effective electrode area, deposition pressure, and the flow rate of a deposition gas containing hydrogen in the deposition conditions can be selected as appropriate.

A semiconductor device capable of holding analog data is provided. Two holding circuits, two bootstrap circuits, and one source follower circuit are formed with use of four transistors and two capacitors. A memory node is provided in each of the two holding circuits; a data potential is written to one of the memory nodes and a reference potential is written to the other of the memory nodes. At the time of data reading, the potential of the one memory node is increased in one of the bootstrap circuits, and the potential of the other memory node is increased in the other of the bootstrap circuits. A potential difference between the two memory nodes is output by the source follower circuit. With use of the source follower circuit, the output impedance can be reduced.

A semiconductor device in which variations in characteristics, deterioration of elements, and abnormality in shape are inhibited is provided. The semiconductor device includes a first region including a plurality of elements and a second region including a plurality of dummy elements. The second region is provided in an outer edge of the first region, and the element and the dummy element each include an oxide semiconductor. The element and the dummy element have the same structure, and a structure body included in the element and a structure body included in the dummy element are formed with the same material and provided in the same layer. The oxide semiconductor includes In, an element M (M is Al, Ga, Y, or Sn), and Zn.