A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions. The method also includes forming channel structures extending vertically through the dielectric stack, replacing the sacrificial layers and sacrificial portions with conductor layers and conductor portions through the at least one slit structure, and forming a source structure in each slit structure. The source structure may include an insulating spacer in each slit opening and a source contact in a respective insulating spacer.

A method for forming a 3D memory device is provided. The method includes forming a dielectric stack including interleaved initial insulating layers and initial sacrificial layers over a substrate, and forming at least one slit structure extending vertically and laterally in the dielectric stack and dividing the dielectric stack into block regions. The at least one slit structure each includes slit openings exposing the substrate and an initial support structure between adjacent slit openings. Each block region may include interleaved insulating layers and sacrificial layers, and the initial support structure may include interleaved insulating portions and sacrificial portions. Each insulating portion and sacrificial portion may be in contact with respective insulating layers and sacrificial layers of a same level from adjacent block regions. The method also includes forming channel structures extending vertically through the dielectric stack, replacing the sacrificial layers and sacrificial portions with conductor layers and conductor portions through the at least one slit structure, and forming a source structure in each slit structure. The source structure may include an insulating spacer in each slit opening and a source contact in a respective insulating spacer.

A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.

A semiconductor device includes a first stacked structure and a second stacked structure spaced apart from each other on a substrate, and a plurality of separation structures and a plurality of vertical memory structures alternately arranged between the first stacked structure and the second stacked structure in a first direction parallel to an upper surface of the substrate. Each of the first and second stacked structures includes a plurality of interlayer insulating layers and a plurality of gate layers alternately repeatedly stacked on the lower structure. Each of the vertical memory structures includes a first data storage structure facing the first stacked structure and a second data storage structure facing the second stacked structure. Side surfaces of the first and second stacked structures facing the vertical memory structures are concave in a plan view.

A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape.

A semiconductor body device includes a stacked body including a plurality of electrode layers stacked with an insulator interposed, a semiconductor body extending in a stacking direction of the stacked body through the electrode layers and having a pipe shape, a plurality of memory cells being provided at intersecting portions of the semiconductor body with the electrode layers, and a columnar insulating member extending in the stacking direction inside the semiconductor body having the pipe shape.

A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.

There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor device includes: a first stack structure including interlayer insulating layers and first conductive patterns, which are alternately stacked; a second stack structure including a second conductive pattern overlapping with the first stack structure, and a third conductive pattern overlapping with the first stack structure with the second conductive pattern interposed between the first stack structure and the third conductive pattern, the third conductive pattern having an oxidation rate different from that of the second conductive pattern; channel structures penetrating the first stack structure and the second stack structure; and a bit line overlapping with the first stack structure with the second stack structure interposed between the first stack structure and the bit line.

A 3D memory array includes a row of stacks, each stack having alternating gate strips and dielectric strips. Dielectric plugs are disposed between the stacks and define cell areas. A data storage film and a channel film are disposed adjacent the stacks on the sides of the cell areas. The middles of the cell areas are filled with an intracell dielectric. Source lines and drain lines form vias through the intracell dielectric. The source lines and the drain lines are each provided with a bulge toward the interior of the cell area. The bulges increase the areas of the source line and the drain line without reducing the channel lengths. In some of these teachings, the areas of the source lines and the drain lines are increased by restricting the data storage film or the channel layer to the sides of the cell areas adjacent the stacks.

A semiconductor device includes a substrate, an active structure, a memory structure, and a first conductive line. The active structure is disposed on the substrate. The memory structure is disposed over the active structure, and has a lower surface and an upper surface opposite to each other. The memory structure includes a deep via disposed in the memory structure, and extends in an upward direction from the lower surface to terminate at the upper surface. The first conductive line is disposed above the upper surface of the memory structure, and extends in a first lengthwise direction transverse to the upward direction. The first conductive line is electrically connected to the active structure through the deep via. A method for manufacturing the semiconductor device is also disclosed.