According to the one embodiment, a memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes: first and second memory cells stacked above a substrate; a first word line coupled to the first and second memory cells; a first bit line coupled to the first memory cell; and a second bit line coupled to the second memory cell. A first state read operation includes a first read operation for reading data from the first memory cell and a second read operation for reading data from the second memory cell. A first read voltage is applied to the first word line during a first period for executing the first read operation, and a second read voltage is applied to the first word line during a second period for executing the second read operation.

A memory device includes a first signal line, a second signal line, a first memory cell and a plurality of second memory cells. The first memory cell is coupled to the first signal line. Each of the second memory cells has a first terminal coupled to the first signal line through the first memory cell and a second terminal coupled to the second signal line.

A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer, a first pillar, and a second pillar. The plurality of first conductive layers are stacked over the substrate in a first direction. The second conductive layer is disposed over the plurality of first conductive layers. The first pillar extends inside the plurality of first conductive layers in the first direction. The first pillar includes a first semiconductor portion including a first semiconductor of single-crystal. The second pillar extends inside the second conductive layer in the first direction. The second pillar includes an insulating portion serving as an axis including an insulator and a second semiconductor portion which is disposed on an outer circumference of the insulating portion in view of the first direction. The second semiconductor portion is in contact with the first semiconductor portion and includes a second semiconductor of poly-crystal.

A semiconductor memory device includes a substrate, a plurality of first conductive layers, a second conductive layer, a first pillar, and a second pillar. The plurality of first conductive layers are stacked over the substrate in a first direction. The second conductive layer is disposed over the plurality of first conductive layers. The first pillar extends inside the plurality of first conductive layers in the first direction. The first pillar includes a first semiconductor portion including a first semiconductor of single-crystal. The second pillar extends inside the second conductive layer in the first direction. The second pillar includes an insulating portion serving as an axis including an insulator and a second semiconductor portion which is disposed on an outer circumference of the insulating portion in view of the first direction. The second semiconductor portion is in contact with the first semiconductor portion and includes a second semiconductor of poly-crystal.

A 3D semiconductor device including: a first level including a single crystal silicon layer and a plurality of first transistors, the plurality of first transistors each including a single crystal channel; a first metal layer overlaying the plurality of first transistors; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; a second level is disposed above the third metal layer, where the second level includes a plurality of second transistors; a fourth metal layer disposed above the second level; and a connective path between the fourth metal layer and either the third metal layer or the second metal layer, where the connective path includes a via disposed through the second level, where the via has a diameter of less than 800 nm and greater than 5 nm, and where at least one of the plurality of second transistors includes a metal gate.

A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.

A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, an outer peripheral conductive layer, a lower layer conductive layer, and a first contact. The substrate includes a core region and a first region. The outer peripheral conductive layer is provided to surround the core region in the first region. The outer peripheral conductive layer is included in a first layer. The lower layer conductive layer is provided in the first region. The first contact is provided on the lower layer conductive layer to surround the core region in the first region. An upper end of the first contact is included in the first layer. The first contact is electrically connected to the outer peripheral conductive layer.

A three-dimensional semiconductor memory device is provided. A stacked structure is formed on a substrate. The stacked structure includes conductive patterns vertically stacked on the substrate. A selection structure including selection conductive patterns is stacked on the stacked structure. A channel structure penetrates the selection structure and the stacked structure to connect to the substrate. An upper interconnection line crosses the selection structure. A conductive pad is disposed on the channel structure to electrically connect the upper interconnection line to the channel structure. A bottom surface of the conductive pad is positioned below a top surface of the uppermost selection conductive pattern of the selection conductive patterns.

According to an embodiment, a semiconductor memory device includes a plurality of control gate electrodes, a semiconductor layer, and a charge accumulation layer. The plurality of control gate electrodes are provided as a stack above a substrate. The semiconductor layer has as its longitudinal direction a direction perpendicular to the substrate, and faces the plurality of control gate electrodes. The charge accumulation layer is positioned between the control gate electrode and the semiconductor layer. A lower end of the charge accumulation layer is positioned more upwardly than a lower end of a lowermost layer-positioned one of the control gate electrodes.

A semiconductor device according to an embodiment includes: a stacked body including a plurality of first conductive films stacked via an inter-layer insulating film;

a first conductive body contacting the stacked body to extend in a stacking direction; and a plurality of first insulating films in the same layers as the first conductive films and disposed between the first conductive body and the first conductive films, the first conductive body including a projecting part that projects along tops of one of the first insulating films and one of the first conductive films, and a side surface of the projecting part contacting an upper surface of the one of the first conductive films.