A nonvolatile memory device with improved reliability is provided. The nonvolatile memory device comprises a substrate, a mold structure including a plurality of word lines stacked on the substrate, a first word line cut region configured to cut the mold structure, a first channel structure spaced apart from the first word line cut region by a first distance, and disposed in the mold structure and the substrate, and a second channel structure spaced apart from the first word line cut region by a second distance, and disposed in the mold structure and the substrate, wherein the second distance is greater than the first distance, a first width of the first channel structure is different from a second width of the second channel structure, and a first length of the first channel structure is different from a second length of the second channel structure.

A device includes a semiconductor substrate, an interfacial layer, a high-k dielectric layer, a first electrode, and a second electrode. The interfacial layer is over the semiconductor substrate. The high-k dielectric layer is over the interfacial layer. The first electrode is over the high-k dielectric layer. The second electrode is over the interfacial layer. The first electrode laterally surrounds the second electrode in a top view.

The present technology includes a semiconductor memory device. The semiconductor memory device includes a first channel pattern and a second channel pattern each extending in a vertical direction and facing each other, a channel separation pattern formed between the first channel pattern and the second channel pattern and extending in the vertical direction, a stack including conductive patterns each surrounding the first channel pattern, the second channel pattern, and the channel separation pattern and stacked apart from each other in the vertical direction, a first memory pattern disposed between each of the conductive patterns and the first channel pattern, and a second memory pattern disposed between each of the conductive patterns and the second channel pattern.

A manufacturing method of a semiconductor device includes: (a) forming a gate structure for a control gate electrode on a semiconductor substrate; (b) forming a charge storage film so as to cover a first side surface, a second side surface, and an upper surface of the gate structure; (c) forming a conductive film for a memory gate electrode on the charge storage film; (d) removing a part of the charge storage film and a part of the conductive film such that the charge storage film and the conductive film remain in this order on the first side surface and the second side surface of the gate structure, thereby forming the memory gate electrode; and (e) removing apart of the gate structure separate from the first side surface and the second side surface such that a part of the semiconductor substrate is exposed from the gate structure.

The present disclosure relates to a memory device that includes a substrate and source and drain regions formed in the substrate. The memory device includes a gate dielectric formed on the substrate and between the source and drain regions. The memory device also includes a gate structure formed on the gate dielectric and the gate structure has a planar top surface. The memory device further includes a multi-spacer structure that includes first, second, and third spacers. The first spacer is formed on a sidewall of the gate structure and a top surface of one of the source and drain regions. The second spacer is formed on a sidewall of the first spacer and the second spacer has a dielectric constant greater than a dielectric constant of the first spacer. The third spacer is formed on a sidewall of the second spacer and a horizontal surface of the first spacer.

A method of manufacturing a memory structure including the following steps is provided. A spacer layer is formed on sidewalls of gate stack structures. A protective material layer covering the spacer layer and the gate stack structures is formed. A mask material layer is formed on the protective material layer. There is a void located in the mask material layer between two adjacent gate stack structures. A first distance is between a top of the protective material layer and a top of the mask material layer. A second distance is between a top of the void and a top of the mask material layer above the void. A third distance is between a bottom of the void and a bottom of the mask material layer below the void. The first distance is greater than a sum of the second and third distances.

A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a first insulating layer between the semiconductor layer and the first gate electrode layer; a second insulating layer between the first insulating layer and the first gate electrode layer, the second insulating layer having a first portion containing a ferroelectric material; and a first layer between the first insulating layer and the second insulating layer, the first layer containing silicon, nitrogen, and fluorine, the first layer having a first region and a second region between the first region and the second insulating layer, the first layer having a second atomic ratio of nitrogen to silicon in the second region higher than a first atomic ratio of nitrogen to silicon in the first region, and the first layer having fluorine concentration higher than the second region.

Some embodiments relate to an integrated chip that includes a first source/drain region and a second source/drain region disposed in a substrate. A plane that is substantially perpendicular to an upper surface of the substrate traverses the first source/drain region and the second source/drain region. Agate electrode extends over a channel region in the substrate between the first source/drain region and the second source/drain region. The gate electrode is separated from the channel region by way of a charge trapping dielectric structure. The charge trapping dielectric structure includes a tunnel dielectric layer, a charge trapping dielectric layer over the tunnel dielectric layer, and a blocking dielectric layer over the charge trapping dielectric layer. The channel region has a channel width measured perpendicularly to the plane, and the tunnel dielectric layer has different thicknesses at different respective points along the channel width.

A semiconductor memory device, and a method of manufacturing the same, includes a gate stack including an interlayer insulating layers and conductive patterns alternately stacked in a vertical direction on a substrate, a channel structure passing through the gate stack and having an upper end protruding above the gate stack, a memory layer surrounding a sidewall of the channel structure, and a source layer formed on the gate stack. The channel structure includes a core insulating layer extending in a central region of the channel structure in the vertical direction, and a channel layer surrounding a sidewall of the core insulating layer, the channel layer formed to be lower in the vertical direction than the core insulating layer and the memory layer.

Disclosed are novel structures and methods for 3D NVM built with vertical transistors above a logic layer. A first embodiment has a conductive film under the transistors and serving as a common node in a memory block. The conductive film may be from a semiconductor layer used to build the transistors. Metal lines are disposed above the transistors for connection through 3D vias to underlying circuitry. Contact plugs may be formed between transistors and metal lines. The conductive film may be coupled to underlying circuitry through contacts on the conductive film or through interconnect vias underneath the film. A second embodiment has conductive lines disposed under the transistors. Either of conductive lines and metal lines may serve as source lines and the other as bit lines for the memory. For low parasitic resistances, the conductive lines may be shorted to bypass metal lines residing in underlying logic layer.