A method of manufacturing a semiconductor structure and a semiconductor structure are provided. The method includes: providing a semiconductor substrate, and forming a first bit line; forming a support layer on the semiconductor substrate, the support layer including a first oxide layer, a first sacrificial layer, a second oxide layer, a second sacrificial layer, a third oxide layer, a third sacrificial layer and a fourth oxide layer that are stacked; forming, at a position corresponding to the first bit line, an active pillar penetrating through the support layer; removing each of the first sacrificial layer and the third sacrificial layer, and forming a first trench; removing a peripheral wall of the active pillar to form a first annular groove, a size of the first annular groove being greater than a size of the first trench in a vertical direction; forming a P-type filler in the first annular groove.

Charge storage and sensing devices having a tunnel diode operable to sense charges stored in a charge storage structure are provided. In some embodiments, a device includes a substrate, a charge storage device on the substrate, and tunnel diode on the substrate adjacent to the charge storage device. The tunnel diode includes a tunnel diode dielectric layer on the substrate, and a tunnel diode electrode on the tunnel diode dielectric layer. A substrate electrode is disposed on the doped region of the substrate, and the tunnel diode electrode is positioned between the charge storage device and the substrate electrode.

A semiconductor device includes a stack including alternately stacked conductive films and insulating films, wherein the stack includes an opening penetrating the conductive films and the insulating films, and wherein the stack includes a rounded corner that is exposed to the opening. The semiconductor device also includes a first channel film formed in the opening and including a first curved surface surrounding the rounded corner. The semiconductor device further includes a conductive pad formed in the opening, and a second channel film interposed between the first curved surface of the first channel film and the conductive pad.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.

A non-volatile memory (NVM) cell includes a semiconductor wire including a select gate portion and a control gate portion. The NVM cell includes a select transistor formed with the select gate portion and a control transistor formed with the control gate portion. The select transistor includes a gate dielectric layer disposed around the select gate portion and a select gate electrode disposed on the gate dielectric layer. The control transistor includes a stacked dielectric layer disposed around the control gate portion, a gate dielectric layer disposed on the stacked dielectric layer and a control gate electrode disposed on the gate dielectric layer. The stacked dielectric layer includes a first silicon oxide layer disposed on the control gate portion, a charge trapping layer disposed on the first silicon oxide, and a second silicon oxide layer disposed on the charge trapping layer.

A memory device includes a memory cell, a writing transistor, and a reading transistor. The memory cell includes a semiconductor substrate, a tunneling layer, a storage layer, a first electrode, a second electrode, and a third electrode. The tunneling layer is over the semiconductor substrate. The storage layer is on the tunneling layer. The first electrode is on the storage layer. The second electrode is on the tunneling layer. The storage layer has a sidewall facing the second electrode. The third electrode is spaced apart from the second electrode. The writing transistor is electrically connected to the first electrode of the memory cell. The reading transistor is electrically connected to the second electrode of the memory cell.

A flash memory cell includes a rectifying device and a transistor. The rectifying device has an input end coupled to a bit line. The transistor has a charge storage structure. The transistor has a first end coupled to an output end of the rectifying device, the transistor has a second end coupled to a source line, and a control end of the transistor is coupled to a word line.

A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

A memory structure and a manufacturing method for the same are provided. The memory structure includes a charge trapping layer, a first silicon oxynitride tunneling film and a second silicon oxynitride tunneling film. The first silicon oxynitride tunneling film is between the charge trapping layer and the second silicon oxynitride tunneling film. A first atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the first silicon oxynitride tunneling film is 10% to 50%. A second atom concentration ratio of a concentration of a nitrogen atom to a total concentration of an oxygen atom and the nitrogen atom of the second silicon oxynitride tunneling film is 1% to 15%. The concentration of the nitrogen atom of the second silicon oxynitride tunneling film is lower than that of the first silicon oxynitride tunneling film.

Semiconductor memory having both volatile and non-volatile modes and methods of operation. A semiconductor storage device includes a plurality of memory cells each having a floating body for storing, reading and writing data as volatile memory. The device includes a floating gate or trapping layer for storing data as non-volatile memory, the device operating as volatile memory when power is applied to the device, and the device storing data from the volatile memory as non-volatile memory when power to the device is interrupted.