A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

A non-volatile memory device includes a memory cell region and a peripheral circuit region below the memory cell region in a vertical direction. The memory cell region includes an upper substrate, channel structures extending in the vertical direction, and a first upper metal line extending in a first direction. The peripheral circuit region includes a first lower metal line extending in a second direction and a first via structure on the first lower metal line and a second via structure on the first lower metal line, a top surface of the second via being in contact with the upper substrate. The memory cell region further includes a first through-hole via structure passing through the upper substrate and the first via structure, and electrically connecting the first upper metal line to the first lower metal line; and the first upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.

A semiconductor device includes: circuit devices on a first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure on the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate on the upper interconnection structure; gate electrodes between the upper interconnection structure and the second substrate; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode; and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.

A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory elements each provided with a writing transistor and a reading transistor. An oxide semiconductor is used in a semiconductor layer of the writing transistor, whereby a storage capacitor is not necessary or the size of the storage capacitor can be reduced. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, data stored in the memory element is read out.

A memory device with large storage capacity is provided. A NAND memory device includes a plurality of connected memory elements each provided with a writing transistor and a reading transistor. An oxide semiconductor is used in a semiconductor layer of the writing transistor, whereby a storage capacitor is not necessary or the size of the storage capacitor can be reduced. The reading transistor includes a back gate. When a reading voltage is applied to the back gate, data stored in the memory element is read out.

Disclosed are semiconductor devices and electronic systems including the same. The semiconductor device may include a stack structure extending in a first direction and including gate electrodes vertically stacked on a substrate, selection structures horizontally spaced apart on the stack structure, an upper isolation structure between the selection structure and extending in the first direction on the stack structure, and vertical structures penetrating the stack structure and the selection structures. The vertical structures include first vertical structures arranged along the first direction and penetrating portions of the upper isolation structure. Each selection structure includes a selection gate electrode and a horizontal dielectric pattern that surrounds top, bottom, and sidewall surfaces of the selection gate electrode. Each selection gate electrode includes a line part extending in the first direction, and an electrode part vertically protruding from the line part and surrounding at least a portion of each first vertical structure.

Semiconductor devices are provided. The semiconductor devices may include a peripheral circuit structure, a memory cell block arranged on the peripheral circuit structure and including strings, each of which includes a lower select transistor, memory cell transistors, and an upper select transistor connected in series and stacked in a vertical direction, and bit lines on the memory cell block. The bit lines may include a first bit line electrically connected to first to third strings of the strings. The lower select transistors of the first to third strings include first to third lower select gate electrodes, respectively. The second lower select gate electrode may be arranged at a different vertical level from the first lower select gate electrode, and the third lower select gate electrode may be arranged at the same vertical level as the first lower select gate electrode.

A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and including a first stack structure on the substrate and a second stack structure on the first stack structure, a seed layer interposed between the first and second stack structures and extended in a horizontal direction, vertical channel structures that penetrate the stack structure and are in contact with the substrate, and a first contact plug that penetrates the stack structure and is in contact with one of the gate electrodes. The seed layer may include first and second seed patterns enclosing the vertical channel structures and the first contact plug, and the first and second seed patterns may be spaced apart from each other in the horizontal direction.

Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.