There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a metal pattern including a first line part extending in a first direction and a second line part which is connected to the first line part and extends in a second direction to intersect with the first line part, and a source structure which has a trench. The metal pattern is formed in the trench and the source structure is in contact with a sidewall of the metal pattern.

A method for manufacturing a semiconductor device to provide a Metal Insulator Semiconductor Field Effect Transistor (MISFET) in a first region of a semiconductor substrate includes forming a first gate insulating film on the semiconductor substrate in the first region, forming a first gate electrode containing silicon on the first gate insulating film, forming first impurity regions inside the semiconductor substrate so as to sandwich the first gate electrode in the first region, the first impurity regions configuring a part of a first source region and a part of a first drain region, forming a first silicide layer on the first impurity region, forming a first insulating film on the semiconductor substrate so as to cover the first gate electrode and the first silicide layer, polishing the first insulating film so as to expose the first gate electrode, and forming a second silicide layer on the first gate electrode.

Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. A semiconductor device includes a substrate, a cell array structure including a plurality of electrodes stacked on the substrate, a vertical channel structure that penetrates the cell array structure and is connected to the substrate, a conductive pad in an upper portion of the vertical channel structure, an interlayer insulating layer on the cell array structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a first stress release layer between the cell array structure and the bit line on a top surface of the interlayer insulating layer. The first stress release layer includes organosilicon polymer, and a carbon concentration of the first stress release layer is higher than that of the interlayer insulating layer.

Disclosed are a three-dimensional semiconductor memory device and an electronic system including the same. A semiconductor device includes a substrate, a cell array structure including a plurality of electrodes stacked on the substrate, a vertical channel structure that penetrates the cell array structure and is connected to the substrate, a conductive pad in an upper portion of the vertical channel structure, an interlayer insulating layer on the cell array structure, a bit line on the cell array structure, a bit line contact electrically connecting the bit line to the conductive pad, and a first stress release layer between the cell array structure and the bit line on a top surface of the interlayer insulating layer. The first stress release layer includes organosilicon polymer, and a carbon concentration of the first stress release layer is higher than that of the interlayer insulating layer.

A semiconductor memory device includes a first substrate defining a cell array region, a mold structure including a plurality of gate electrodes sequentially spaced and stacked on the first substrate in a step form, and a channel hole defined as penetrating the plurality of gate electrodes on the cell array region in a vertical direction perpendicular to an upper surface of the first substrate. The device includes an information storage layer along side walls and a bottom surface of the channel hole, the information storage layer including a blocking insulation layer along the side walls and the bottom surface of the channel hole, a charge storage layer on the blocking insulation layer, and a tunneling insulation layer. The device includes a channel layer on the information storage layer inside the channel hole, and an insulation pattern arranged to fill the channel hole on the channel layer.

A semiconductor memory device includes a first substrate defining a cell array region, a mold structure including a plurality of gate electrodes sequentially spaced and stacked on the first substrate in a step form, and a channel hole defined as penetrating the plurality of gate electrodes on the cell array region in a vertical direction perpendicular to an upper surface of the first substrate. The device includes an information storage layer along side walls and a bottom surface of the channel hole, the information storage layer including a blocking insulation layer along the side walls and the bottom surface of the channel hole, a charge storage layer on the blocking insulation layer, and a tunneling insulation layer. The device includes a channel layer on the information storage layer inside the channel hole, and an insulation pattern arranged to fill the channel hole on the channel layer.

A semiconductor device includes a stack structure having gate electrodes and interlayer insulating layers, the stack structure having a cell region and a step region, and the gate electrodes extending in a first direction to have a step shape in the step region, channel structures through the stack structure in the cell region, separation structures through the stack structure and extending in the first direction, and support structures between the separation structures and through the stack structure in the step region. The step region includes first and second regions, the first region closer to the cell region in the first direction than the second region is, the support structures include first and second support structures through the stack structure in the first and second regions, respectively, a maximum width of the first support structure being greater than that of the second support structure.

A semiconductor device includes a stack structure having gate electrodes and interlayer insulating layers, the stack structure having a cell region and a step region, and the gate electrodes extending in a first direction to have a step shape in the step region, channel structures through the stack structure in the cell region, separation structures through the stack structure and extending in the first direction, and support structures between the separation structures and through the stack structure in the step region. The step region includes first and second regions, the first region closer to the cell region in the first direction than the second region is, the support structures include first and second support structures through the stack structure in the first and second regions, respectively, a maximum width of the first support structure being greater than that of the second support structure.

Vertical wordline driver structures and methods. The vertical wordline driver comprises a transistor that is used to drive a wordline in a three-dimensional 3D memory structure. A vertical transistor structure is formed in a semiconductor substrate comprising a gate all around (GAA) structure or a double-gate structure including a gate oxide, an amorphous IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide, and a liner adjacent to the amorphous IGZO channel. The GAA structure may comprise a conical frustrum shape or a cylindrical shape with straight walls. The double-gate structure may have straight or angled walls. An outer wall of the gate oxide is in contact with a polysilicon gate layer. An upper and lower contact is electrically coupled to the amorphous IGZO channel.

Vertical wordline driver structures and methods. The vertical wordline driver comprises a transistor that is used to drive a wordline in a three-dimensional 3D memory structure. A vertical transistor structure is formed in a semiconductor substrate comprising a gate all around (GAA) structure or a double-gate structure including a gate oxide, an amorphous IGZO (Indium Gallium Zinc Oxide) channel, adjacent to the gate oxide, and a liner adjacent to the amorphous IGZO channel. The GAA structure may comprise a conical frustrum shape or a cylindrical shape with straight walls. The double-gate structure may have straight or angled walls. An outer wall of the gate oxide is in contact with a polysilicon gate layer. An upper and lower contact is electrically coupled to the amorphous IGZO channel.