A non-volatile memory device includes a first semiconductor layer and a second semiconductor layer arranged in the vertical direction. A first semiconductor layer includes a plurality of memory cells, and a plurality of metal lines extending in a first direction, and including first bit lines, second bit lines, and a common source line tapping wire between the first bit lines and the second bit lines. A second semiconductor layer includes a page buffer circuit connected to the first bit lines and the second bit lines, and the page buffer circuit includes first transistors arranged below the first bit lines and electrically connected to the first bit lines, second transistors arranged below the second bit lines and electrically connected to the second bit lines, and a first guard ring arranged below and overlapped the common source line tapping wire in the vertical direction and extending in the first direction.

A method of forming a microelectronic device comprises forming a microelectronic device structure comprising a base structure, a doped semiconductive material overlying the base structure, a stack structure overlying the doped semiconductive material, cell pillar structures vertically extending through the stack structure and the doped semiconductive material and into the base structure, and digit line structures vertically overlying the stack structure. An additional microelectronic device structure comprising control logic devices is formed. The microelectronic device structure is attached to the additional microelectronic device structure to form a microelectronic device structure assembly. The base structure and portions of the cell pillar structures vertically extending into the base structure are removed to expose the doped semiconductive material. The doped semiconductive material is then patterned to form at least one source structure over the stack structure and coupled to the cell pillar structures. Microelectronic devices and electronic systems are also described.

Integrated circuitry comprises two three-dimensional (3D) array regions individually comprising tiers of electronic components. A stair-step region is between the two 3D-array regions. First stair-step structures alternate with second stair-step structures along a first direction within the stair-step region. The first stair-step structures individually comprise two opposing first flights of stairs in a first vertical cross-section along the first direction. The stairs in the first flights each have multiple different-depth treads in a second vertical cross-section that is along a second direction that is orthogonal to the first direction. The second stair-step structures individually comprise two opposing second flights of stairs in the first vertical cross-section. The stairs in the second flights each have only a single one tread along the second direction. Other embodiments, including method, are disclosed.

A three-dimensional semiconductor devices including a substrate, a stack structure including gate electrodes on the substrate and string selection electrodes spaced apart from each other on the gate electrodes, a first separation structure running in a first direction across the stack structure and being between the string selection electrodes, vertical channel structures penetrating the stack structure, and bit lines connected to the vertical channel structures and extending in a second direction may be provided. A first subset of the vertical channel structures is connected in common to one of the bit lines. The vertical channel structures of the first subset may be adjacent to each other in the second direction across the first separation structure. Each of the string selection electrodes may surround each of the vertical channel structures of the first subset.

A semiconductor device including a substrate including first, second, and third regions; a peripheral circuit structure on the substrate and including a peripheral circuit and wiring layers connected to the peripheral circuit; a common source plate on the peripheral circuit structure and extending in a horizontal direction; gate electrodes on the common source plate on the first and second regions, spaced apart from each other in a first direction perpendicular to an upper surface of the substrate, the gate electrodes having a stair shape on the second region; a channel structure extending in the first direction through the gate electrodes on the first region; a first conductive through-via penetrating the common source plate on the third region and electrically connected to the wiring layers; and a dummy insulating pillar adjacent to the first conductive through-via on the third region and connected to an upper surface of the common source plate.

A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of insulation layers and a plurality of electrode layers alternately stacked in a third direction intersecting with first and second directions. A plurality of channel structures extends through the stacked structure in the third direction. A first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. A second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. Each of the plurality of first and second horizontal wirings are connected to corresponding one of the plurality of channel structures. A first line identifier is disposed between the first wiring group and the second wiring group.

A semiconductor device includes a stacked structure disposed on a substrate. The stacked structure includes a plurality of insulation layers and a plurality of electrode layers alternately stacked in a third direction intersecting with first and second directions. A plurality of channel structures extends through the stacked structure in the third direction. A first wiring group includes a plurality of first horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. A second wiring group includes a plurality of second horizontal wirings disposed on the stacked structure that are arranged in the first direction and extends in the second direction. Each of the plurality of first and second horizontal wirings are connected to corresponding one of the plurality of channel structures. A first line identifier is disposed between the first wiring group and the second wiring group.

In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a first doped region formed below the first trench isolation, a second doped region formed in the substrate, and a first gate structure formed adjacent to the second doped region. The first doped region is an ion implantation region, and a distance between the first doped region and the second doped region is equal to or more than 0.6 μm.

In certain aspects, a semiconductor device includes a substrate, a first trench isolation in the substrate, a first doped region formed below the first trench isolation, a second doped region formed in the substrate, and a first gate structure formed adjacent to the second doped region. The first doped region is an ion implantation region, and a distance between the first doped region and the second doped region is equal to or more than 0.6 μm.

Embodiments of contact structures of a three-dimensional memory device and fabrication method thereof are disclosed. The three-dimensional memory structure includes a film stack disposed on a substrate, wherein the film stack includes a plurality of conductive and dielectric layer pairs, each conductive and dielectric layer pair having a conductive layer and a first dielectric layer. The three-dimensional memory structure also includes a staircase structure formed in the film stack, wherein the staircase structure includes a plurality of steps, each staircase step having two or more conductive and dielectric layer pairs. The three-dimensional memory structure further includes a plurality of coaxial contact structures formed in a first insulating layer over the staircase structure, wherein each coaxial contact structure includes one or more conductive and insulating ring pairs and a conductive core, each conductive and insulating ring pair having a conductive ring and an insulating ring.