A three-dimensional semiconductor memory device including a first peripheral circuit including different decoder circuits, a first memory on the first peripheral circuit, the first memory including a first stack structure having first electrode layers stacked on one another and first inter-electrode dielectric layers therebetween, a first planarized dielectric layer covering an end of the first stack structure, and a through via that penetrates the end of the first stack structure, the through via electrically connected to one of the decoder circuits, and a second memory on the first memory and including a second stack structure having second electrode layers stacked on one another and second inter-electrode dielectric layers therebetween, a second planarized dielectric layer covering an end of the second stack structure, and a cell contact plug electrically connecting one of the second electrode layers to the through via.

A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

A semiconductor device includes a substrate including a lower horizontal layer and an upper horizontal layer and having a cell array region and a connection region, an electrode structure including electrodes, which are stacked above the substrate, and which extend from the cell array region to the connection region, a vertical channel structure on the cell array region that penetrates the electrode structure and is connected to the substrate, and a separation structure on the connection region that penetrates the electrode structure. The lower horizontal layer has a first top surface in contact with a first portion of the separation structure, and a second top surface in contact with a second portion of the separation structure, and an inflection point at which a height of the lower horizontal layer is abruptly changed between the first top surface and the second top surface.

Some embodiments include apparatuses and methods of fabricating the apparatuses. One of the apparatuses includes a substrate of a semiconductor die; a memory cell portion located over a first portion of the substrate; a conductive pad portion located over a second portion of the substrate and outside the memory cell portion; and a sensor circuit including a portion located over the second portion of the substrate and under the conductive pad portion. The conductive pad portion includes conductive pads. Each of the conductive pads is part of a respective electrical path coupled to a conductive contact of a base outside the substrate.

A semiconductor memory device is disclosed. The device includes a peripheral circuit structure on a substrate, a semiconductor layer on the peripheral circuit structure, an electrode structure on the semiconductor layer, the electrode structure including electrodes stacked on the semiconductor layer, a vertical channel structure penetrating the electrode structure and being connected to the semiconductor layer, a separation structure penetrating the electrode structure, extending in a first direction, and horizontally dividing the electrode of the electrode structure into a pair of electrodes, an interlayered insulating layer covering the electrode structure, and a through contact penetrating the interlayered insulating layer and being electrically connected to the peripheral circuit structure.

Disclosed are semiconductor devices and semiconductor packages. The semiconductor device comprises a semiconductor substrate that includes a stack region and a pad region, a peripheral circuit structure that includes a plurality of peripheral circuits on the semiconductor substrate, a cell array structure on the peripheral circuit structure, and a redistribution layer on the cell array structure and including a redistribution dielectric layer and a redistribution pattern on the redistribution dielectric layer. The redistribution dielectric layer covers an uppermost conductive pattern of the cell array structure. The redistribution pattern is connected to the uppermost conductive pattern. A thickness in a vertical direction of the redistribution layer on the pad region is greater than that of the redistribution layer on the stack region.

Disclosed are semiconductor devices and semiconductor packages. The semiconductor device comprises a semiconductor substrate that includes a stack region and a pad region, a peripheral circuit structure that includes a plurality of peripheral circuits on the semiconductor substrate, a cell array structure on the peripheral circuit structure, and a redistribution layer on the cell array structure and including a redistribution dielectric layer and a redistribution pattern on the redistribution dielectric layer. The redistribution dielectric layer covers an uppermost conductive pattern of the cell array structure. The redistribution pattern is connected to the uppermost conductive pattern. A thickness in a vertical direction of the redistribution layer on the pad region is greater than that of the redistribution layer on the stack region.

In certain aspects, a memory device includes an array of memory cells and a plurality of peripheral circuits coupled to the array of memory cells. The peripheral circuits include a first peripheral circuit including a recess gate transistor. The peripheral circuits also include a second peripheral circuit including a flat gate transistor.

In certain aspects, a method for forming a three-dimensional (3D) memory device is disclosed. A first semiconductor structure including an array of NAND memory strings is formed on a first substrate. A second semiconductor structure including a recess gate transistor is formed on a second substrate. The recess gate transistor includes a recess gate structure protruding into the second substrate. The first semiconductor structure and the second semiconductor structure are bonded in a face-to-face manner, such that the array of NAND memory strings is coupled to the recess gate transistor across a bonding interface.

A three-dimensional 3D memory device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes a first semiconductor layer and an array of NAND memory strings. The second semiconductor structure is under a second side of the first semiconductor layer. The second side of the first semiconductor layer is opposite to the first side of the first semiconductor layer. The second semiconductor structure includes a second semiconductor layer, a first peripheral circuit, and a second peripheral circuit. The first peripheral circuit includes a first transistor in contact with a first side of the second semiconductor layer. The second peripheral circuit includes a second transistor in contact with a second side of the second semiconductor layer. The second side of the second semiconductor layer is opposite to the first side of the second semiconductor layer.