Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a 3D memory device includes a first semiconductor assembly, a second semiconductor assembly, and an inter-assembly bonding layer between the first semiconductor assembly and the second semiconductor assembly. The first semiconductor assembly includes a first array structure and a first periphery structure. The first array structure includes a first memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The first periphery structure includes a plurality of first peripheral circuits electrically connected to the first memory stack. The second semiconductor assembly includes a second array structure and a second periphery structure. The second array structure includes a second memory stack having a plurality of interleaved stack conductive layers and stack dielectric layers. The second periphery structure includes a plurality of second peripheral circuits electrically connected to the second memory stack.

In certain aspects, a three-dimensional (3D) memory device includes a first semiconductor structure, a second semiconductor structure, and a bonding interface between the first and second semiconductor structures. The first semiconductor structure includes an array of NAND memory strings, a first peripheral circuit of the array of NAND memory strings including a first transistor, a polysilicon layer between the array of NAND memory strings and the first peripheral circuit, and a first semiconductor layer in contact with the first transistor. The polysilicon layer is in contact with sources of the array of NAND memory strings. The second semiconductor structure includes a second peripheral circuit of the array of NAND memory strings including a second transistor, and a second semiconductor layer in contact with the second transistor. The second semiconductor layer is between the bonding interface and the second peripheral circuit. The polysilicon layer is between the first semiconductor layer and the second semiconductor layer.

An integrated circuit device according to the inventive concept includes: a semiconductor substrate including a cell region and a connection region; a gate stack including a plurality of gate electrodes and a plurality of insulating layers extending on a main surface of the semiconductor substrate in a horizontal direction and alternately stacked thereon in a vertical direction, the gate stack having a stair structure in the connection region; and a plurality of contact plugs in the connection region, wherein, in a portion of the connection region, a first length, in the horizontal direction, of a first gate electrode that is located in the lowest layer among the plurality of gate electrodes is less than a second length, in the horizontal direction, of a second gate electrode that is located above the first gate electrode.

There is a method of manufacturing a memory device. The method includes forming a mask layer on an etching target layer; forming, on the mask layer, a compensation layer with a second impurity that chemically bonds to the mask layer with a first impurity; performing a first etching process that patterns the compensation layer and the mask layer to form a mask pattern; and performing a second etching process that etches the etching target layer, which is exposed through openings of the mask pattern.

A semiconductor device includes a first structure having first and second memory regions, an extension region therebetween, and word lines; and a second structure having a circuit region overlapping the extension region. The word lines include first and second common word lines at different levels, and first and second intermediate individual word lines at a same level and spaced apart. Each of the first and second common word lines are in the first and second memory regions and the extension region. The first intermediate individual word line is in the first memory region and extends into the extension region at a level between the first and second common word lines. The second intermediate individual word line is in the second memory region and extends into the extension region. The circuit region includes pass transistors connected to the word lines. A pass transistor overlaps the word lines in the extension region.

A semiconductor device includes a first structure including a peripheral circuit and a second structure on the first structure. The second structure includes: a stack structure including first and second stack structures; separation structures passing through the first stack structure; a memory vertical structure between the separation structures and passing through the first stack structure; and a capacitor including first and second capacitor electrodes passing through the second stack structure and extending parallel to each other. The first stack structure includes spaced apart gate electrodes and interlayer insulating layers alternately stacked therewith. The second stack structure includes spaced apart first insulating layers, and second insulating layers alternately stacked therewith. Each of the first and second capacitor electrodes has a linear shape. The first and second insulating layers include a different material from each other. The second insulating layers include the same material as the interlayer insulating layers.

Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

Some embodiments include a memory device and methods of forming the memory device. One such memory device includes a first group of memory cells, each of the memory cells of the first group being formed in a cavity of a first control gate located in one device level of the memory device. The memory device also includes a second group of memory cells, each of the memory cells of the second group being formed in a cavity of a second control gate located in another device level of the memory device. Additional apparatus and methods are described.

Provided herein is a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a contact pattern including a vertical contact part, and a sidewall contact part extending from the vertical contact part in a direction crossing the vertical contact part, a lower conductive pattern having a hole into which the vertical contact part is inserted, and an upper conductive pattern overlapping a portion of the lower conductive pattern. The upper conductive pattern includes a first side portion in contact with the sidewall contact part, and a second side portion facing the vertical contact part and spaced apart from the vertical contact part.