A three-dimensional memory device includes a vertical repetition of multiple instances of a unit layer stack, memory openings vertically extending through the vertical repetition, and memory opening fill structures located within the memory openings. Each of the memory opening fill structures contains a respective vertical stack of memory elements. The unit layer stack includes, from bottom to top or from top to bottom, a cavity-free insulating layer that is free of any cavity therein, a first-type electrically conductive layer, a cavity-containing insulating layer including an encapsulated cavity therein, and a second-type electrically conductive layer.

A semiconductor device and a data storage system, the device including a lower structure; and an upper structure on the lower structure and including a memory cell array, wherein the lower structure includes a semiconductor substrate, first and second active regions spaced apart from each other in a first direction on the semiconductor substrate, the first and second active regions being defined by an isolation insulating layer on the semiconductor substrate, and first and second gate pattern structures extending in the first direction to cross the first and second active regions, respectively, on the semiconductor substrate, the first gate pattern structure and the second gate pattern structure have first and second end portions spaced apart from each other in a facing manner in the first direction, respectively, and the first and second end portions are concavely curved in opposite directions away from each other in a plan view.

A semiconductor device includes a stacked film including a plurality of electrode layers and a plurality of insulating layers alternately stacked in a first direction and a columnar portion including a charge storage layer and a first semiconductor layer and extending in the first direction in the stacked film. The device further includes a second semiconductor layer provided on the stacked film and the columnar portion, and at least a part of regions in the second semiconductor layer contains phosphorus having an atomic concentration of 1.0×10.sup.21/cm.sup.3 or more and hydrogen having an atomic concentration of 1.0×10.sup.19/cm.sup.3 or less.

Embodiments of three-dimensional (3D) memory devices having through array contacts (TACs) and methods for forming the same are disclosed. In an example, a method for forming a 3D memory device is disclosed. A dielectric stack including interleaved a plurality of dielectric layers and a plurality of sacrificial layers is formed above a substrate. A channel structure extending vertically through the dielectric stack is formed. A first opening extending vertically through the dielectric stack is formed. A spacer is formed in a plurality of shallow recesses and on a sidewall of the first opening. The plurality of shallow recesses abut the sidewall of the first opening. A TAC extending vertically through the dielectric stack is formed by depositing a conductor layer in contact with the spacer in the first opening. A slit extending vertically through the dielectric stack is formed.

In certain aspects, a three-dimensional (3D) memory device includes a plurality of channel structures in a first region, a staircase structure in a second region, and a word line extending in the first region and the second region. The first region and the second region are arranged along a first direction. The word line is discontinuous in the first direction between the first region and the second region.

An embodiment of a memory device may include a full block memory array of a lower tile of 3D NAND string memory cells, a full block memory array of an upper tile of 3D NAND string memory cells, a first portion of a string driver circuit coupled to the full block memory array of the lower tile, a second portion of the string driver circuit coupled to the full block memory array of the upper tile, a first split block memory array of the lower tile coupled to the first portion of the string driver circuit, and a second split block memory array of the upper tile coupled to the second portion of the string driver circuit. Other embodiments are disclosed and claimed.

The present technology relates to a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device includes a stack structure including a plurality of interlayer insulating layers and a plurality of gate conductive layers that are alternately stacked, a channel plug at least partially passing through the stack structure on a cell region, and a plurality of support structures at least partially passing through the stack structure on a contact region.

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a conductive gate contact penetrating a contact region of a stepped stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked.

A memory device includes a first stack structure, a second stack structure, a channel pillar, a storage layer, and a conductive pillar. The first stack structure includes a first insulating layer and a first conductive layer located on the first insulating layer. The second stack structure is located on the first stack structure and includes a plurality of second conductive layers and a plurality of second insulating layers which alternate with each other. The channel pillar penetrates through the second stack structure and extends to the first stack structure. The storage layer is located between the channel pillar and the first stack structure and between the channel pillar and the second stack structure. The conductive pillar is located in the first conductive layer and electrically connected to the first conductive layer and the substrate.

A semiconductor device includes a substrate having a first region and a second region, gate electrodes stacked and spaced apart from each other in a first direction perpendicular to an upper surface of the second substrate, and extending by different lengths in a second direction on the second region to have pad regions in which upper surfaces thereof are exposed, channel structures penetrating the gate electrodes, extending in the first direction, and respectively including a channel layer, on the first region, contact plugs penetrating the pad regions of the gate electrodes and extending in the first direction, and contact insulating layers surrounding the contact plugs. The gate electrodes have side surfaces protruding further toward the contact plugs in the pad regions than ones of the gate electrodes therebelow.