A semiconductor device includes a substrate having a first region and a second region, a first stack structure in the first region, a first channel structure penetrating through the first stack structure and in contact with the substrate, and a second stack structure on the first stack structure and the first channel structure. The device includes a second channel structure penetrating through the second stack structure and connected to the first channel structure, a first molding structure in the second region, a first alignment structure penetrating through the first molding structure and in contact with the substrate, and a second molding structure on the first molding structure and the first alignment structure. The device includes a second alignment structure penetrating through the second molding structure and connected to the first alignment structure, and a protective layer between the first molding structure and the second molding structure.

A method for manufacturing a cured product pattern of a curable composition includes the steps of, in sequence, depositing a droplet of the curable composition onto a substrate; bringing a mold having an uneven pattern formed in a surface thereof into contact with the curable composition; curing the curable composition; and releasing a cured product of the curable composition from the mold. The mold has a recess having a bottom surface and a stair structure arranged to form an opening surface that becomes wider from the bottom surface toward the surface of the mold. In the contact step, the curable composition comes into contact with the stair portion after a top of the droplet comes into contact with the bottom surface.

A non-volatile memory device includes a memory cell region and a peripheral circuit region below the memory cell region in a vertical direction. The memory cell region includes an upper substrate, channel structures extending in the vertical direction, and a first upper metal line extending in a first direction. The peripheral circuit region includes a first lower metal line extending in a second direction and a first via structure on the first lower metal line and a second via structure on the first lower metal line, a top surface of the second via being in contact with the upper substrate. The memory cell region further includes a first through-hole via structure passing through the upper substrate and the first via structure, and electrically connecting the first upper metal line to the first lower metal line; and the first upper metal line is electrically connected to the upper substrate through the first through-hole via structure, the first lower metal line, and the second via structure.

A semiconductor device includes: circuit devices on a first substrate; a lower interconnection structure electrically connected to the circuit devices; a lower bonding structure connected to the lower interconnection structure; an upper bonding structure on the lower bonding structure; an upper interconnection structure connected to the upper bonding structure; a second substrate on the upper interconnection structure; gate electrodes between the upper interconnection structure and the second substrate; channel structures penetrating the gate electrodes and each including a channel layer; via patterns on the second substrate; a source contact plug spaced apart from the second substrate on an external side of the second substrate and having an upper surface higher than the second substrate and a lower surface lower than a lowermost gate electrode; and a source connection pattern contacting upper surfaces of each of the via patterns and the upper surface of the source contact plug.

A pick-up structure for a memory device and method for manufacturing memory device are provided. The pick-up structure includes a substrate and a plurality of pick-up electrode strips. The substrate has a memory cell region and a peripheral pick-up region adjacent thereto. The pick-up electrode strips are parallel to a first direction and arranged on the substrate in a second direction. The second direction is different from the first direction. Each pick-up electrode strip includes a main part in the peripheral pick-up region and an extension part extending from the main part to the memory cell region. The main part is defined by fork-shaped patterns of a first mask layer. The extension part has a width less than that of the main part, and the extension part has a side wall surface aligned with a side wall surface of the main part.

A three-dimensional semiconductor memory device may include a substrate, a stack structure including interlayer dielectric layers and gate electrodes alternately and repeatedly stacked on the substrate and including a first stack structure on the substrate and a second stack structure on the first stack structure, a seed layer interposed between the first and second stack structures and extended in a horizontal direction, vertical channel structures that penetrate the stack structure and are in contact with the substrate, and a first contact plug that penetrates the stack structure and is in contact with one of the gate electrodes. The seed layer may include first and second seed patterns enclosing the vertical channel structures and the first contact plug, and the first and second seed patterns may be spaced apart from each other in the horizontal direction.

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a device including tiers of materials located one over another, the tiers of materials including respective memory cells and control gates for the memory cells. The control gates include respective portions that collectively form part of a staircase structure. The staircase structure includes first regions and second regions coupled to the first regions. The second regions include respective sidewalls in which a portion of each of the first regions and a portion of each of the second regions are part of a respective control gate of the control gates. The device also includes conductive pads electrically separated from each other and located on the first regions of the staircase structure, and conductive contacts contacting the conductive pads.

A three-dimensional memory device includes vertical layer stacks that are laterally spaced apart by backside trenches that laterally extend along a first horizontal direction, where each of the vertical layer stacks includes a respective alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stacks, memory opening fill structures located in the memory openings and including a respective vertical stack of memory elements and a respective vertical semiconductor channel, and backside trench fill structures located within a respective one of the backside trenches. Each of the backside trench fill structures includes a plurality of dielectric bridge structures laterally spaced apart along the first horizontal direction and dielectric fin portions located at levels of a plurality of the electrically conductive layers. The dielectric fin portions laterally protrude outward relative to sidewalls of the insulating layers within the respective neighboring pair of alternating stacks.

Disclosed are three-dimensional semiconductor memory devices, methods of manufacturing the same, and electronic systems including the same. The device includes a peripheral circuit structure on a substrate, and a cell array structure including a stack structure that includes gate electrodes on the peripheral circuit structure, a first source conductive pattern on the stack structure, and vertical channel structures in vertical channel holes that penetrate the stack structure and the first source conductive pattern. The vertical channel structure includes a data storage pattern on a sidewall of the vertical channel hole, a vertical semiconductor pattern on the data storage pattern, and a second source conductive pattern on the vertical semiconductor pattern and surrounded by the data storage pattern. A thickness of the data storage pattern between the first source conductive pattern and the second source conductive pattern is greater than it is between the stack structure and the vertical semiconductor pattern.

There are provided a semiconductor memory device and a manufacturing method of the semiconductor memory device. The semiconductor memory device includes a metal pattern including a first line part extending in a first direction and a second line part which is connected to the first line part and extends in a second direction to intersect with the first line part, and a source structure which has a trench. The metal pattern is formed in the trench and the source structure is in contact with a sidewall of the metal pattern.