An apparatus, a method and a system. The apparatus comprises a memory array including word lines defining a staircase structure, and a staircase etch stop layer including: a sandwich etch stop layer disposed on a top region the staircase and including a first etch stop layer and a third etch stop layer of a first material, and a second etch stop layer sandwiched between the first etch stop layer and the third etch stop layer and made of a second material having etch properties different from the first material; a precut etch stop layer disposed at a region of the staircase structure below the top region and including the second etch stop layer and the third etch stop layer and not the first etch stop layer; and contact structures extending through a dielectric layer and the staircase etch stop layer and landing on the word lines at the staircase structure.

A 3D-NAND memory includes a transistor formed in a first side of a periphery circuit substrate, a memory cell stack formed over a first side of a cell array substrate, and a first connection structure formed over an opposing second side of the cell array substrate. The memory cell stack includes a doped region formed in the first side of the cell array substrate and coupled to the first connection structure through a first VIA, a common source structure that extends from the doped region toward the first side of the periphery circuit substrate, and a second connection structure that is positioned over and coupled to the common source structure. The first side of the cell array substrate and the first side of the periphery circuit substrate are aligned facing each other so that the transistor is coupled to the second connection structure.

A semiconductor memory device includes a stacked structure including a plurality of conductive layers and a plurality of interlayer insulating layers, which are alternately stacked on a substrate; stepped grooves provided in the stacked structure, the stepped grooves having different depths from each other; and an opening portion penetrating the stacked structure to contact the substrate and having steps on sidewalls, the steps having heights corresponding to depth differences between stepped grooves.

A three-dimensional semiconductor memory device includes a substrate including a first connection region and a second connection region in a first direction and a cell array region between the first and second connection regions, and a first block structure on the substrate. The first block structure has a first width on the cell array region, the first block structure has a second width on the first connection region, and the first block structure has a third width on the second connection region. The first, second and third widths are parallel to a second direction intersecting the first direction, and the first width is less than the second width and is greater than the third width.

A semiconductor memory device includes a controller which executes a read operation. In the read operation, the controller applies first and second read voltages to a word line, reads data at each of first and second times, applies the first voltage to a source line at each of the first and second times, applies a second voltage to the source line during the application of the first read voltage to the word line and before the first time, and applies a third voltage to the source line during the application of the second read voltage to the word line and before the second time.

A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The operative channel-material strings in the laterally-spaced memory blocks comprise part of a memory plane. An elevationally-extending wall is in the memory plane laterally-between immediately-laterally-adjacent of the memory blocks and that completely encircles an island that is laterally-between immediately-laterally-adjacent of the memory blocks in the memory plane. Other embodiments, including method are disclosed.

A semiconductor storage device includes: a substrate having a front surface; a plurality of conductive layers arranged in a first direction, the first direction intersecting the front surface of the substrate; a plurality of memory cells connected to the plurality of conductive layers; a contact electrode extending in the first direction and connected to one of the plurality of conductive layers; and an insulating structure extending in the first direction, the insulating structure connected to an end portion of the contact electrode on one side of the contact electrode in the first direction, and penetrating the plurality of conductive layers.

In one embodiment, a semiconductor device includes a substrate, and a plurality of insulating layers provided on the substrate. The device further includes a plurality of electrode layers provided on the substrate alternately with the plurality of insulating layers and including metal atoms and impurity atoms different from the metal atoms, lattice spacing between the metal atoms in the electrode layers being greater than lattice spacing between the metal atoms in an elemental substance of the metal atoms.

A semiconductor memory device including: a common source line; a substrate on the common source line; a plurality of gate electrodes arranged on the substrate and spaced apart from each other in a first direction perpendicular to a top surface of the common source line; a plurality of insulation films arranged among the plurality of gate electrodes; a plurality of channel structures penetrating through the plurality of gate electrodes and the plurality of insulation films in the first direction; and a plurality of residual sacrificial films arranged on the substrate and spaced apart from each other in the first direction, wherein the plurality of gate electrodes are disposed on opposite sides of the plurality of residual sacrificial films.

A semiconductor memory device, with which a manufacturing method is associated, includes a substrate. The semiconductor memory device also includes a source structure disposed on a first region of the substrate, memory cell strings connected to the source structure, and a capacitor structure disposed on a second region of the substrate. The capacitor structure is spaced apart from the source structure in a horizontal direction.