A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.

Methods of fabricating a semiconductor devices are disclosed. The method include forming a transistor device in a first device region on the semiconductor device, and forming a memory device in a second device region on the semiconductor device, the memory device being connected to the transistor device. In some embodiments, forming the memory device includes forming a first bit line, forming a first word line connected to the first bit line, forming a plate line connected to the first word line and the first bit line, forming a second bit line connected to the plate line, and forming a second word line connected to the second bit line and the plate line.

A thin film transistor includes an active layer located over a substrate, a first gate stack including a stack of a first gate dielectric and a first gate electrode and located on a first surface of the active layer, a pair of first contact electrodes contacting peripheral portions of the first surface of the active layer and laterally spaced from each other along a first horizontal direction by the first gate electrode, a second contact electrode contacting a second surface of the active layer that is vertically spaced from the first surface of the active layer, and a pair of second gate stacks including a respective stack of a second gate dielectric and a second gate electrode and located on a respective peripheral portion of a second surface of the active layer.

A non-volatile memory device is provided. The nonvolatile memory device includes a metal pillar, a channel layer separated from the metal pillar and surrounding a side surface of the metal pillar, a source arranged on one end of the channel layer, a drain arranged on the other end of the channel layer, a gate insulating layer surrounding a side surface of the channel layer, and a plurality of insulating elements and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer and surrounding a side surface of the gate insulating layer.

A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low- cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.

A semiconductor device includes a substrate including, in a first area, a first semiconductor channel and coupled to a portion of a first memory layer, and first, second, and third conductive structures. The first and third conductive structures are coupled to end portions of a sidewall of the first semiconductor channel, with the second conductive structure coupled to a middle portion of the sidewall. The semiconductor device includes, in a second area, a second semiconductor channel and coupled to a first portion of a second memory layer, and fourth and fifth conductive structures. The fourth and fifth conductive structures are coupled to end portions of a sidewall of the second semiconductor channel, with no vertically extending conductive structure interposed between the fourth and fifth conductive structures.

A semiconductor memory device comprises: a substrate; a first semiconductor portion provided separated from the substrate in a first direction intersecting a surface of the substrate, the first semiconductor portion extending in a second direction intersecting the first direction; a first gate electrode extending in the first direction; a first insulating portion which is provided between the first semiconductor portion and the first gate electrode, includes hafnium (Hf) and oxygen (O), and includes an orthorhombic crystal as a crystal structure; a first conductive portion provided between the first semiconductor portion and the first insulating portion; and a second insulating portion provided between the first semiconductor portion and the first conductive portion. An area of a facing surface of the first conductive portion facing the first semiconductor portion is larger than an area of a facing surface of the first conductive portion facing the first gate electrode.

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.