A memory device according to an embodiment includes a semiconductor layer, a gate electrode layer, and a first dielectric layer provided between the semiconductor layer and the gate electrode layer. The first dielectric layer contains aluminum (Al), a first element, nitrogen (N), and silicon (Si). The first element is at least one element selected from the group consisting of scandium (Sc), yttrium (Y), lanthanoid (Ln), boron (B), gallium (Ga), and indium (In).

[Object] To provide a semiconductor element capable of realizing an element having a nonvolatile memory capable of stably storing highly integrated data, a nonvolatile memory device, a multiply-accumulate operation device, and a method of manufacturing the semiconductor element. [Solving means] A semiconductor element according to an embodiment of the present technology includes a plurality of cell blocks. The plurality of cell blocks are configured by connecting a plurality of cell portions in series with each other, the plurality of cell portions each having a MOSFET for controlling conduction of a channel portion and a resistor connected in parallel to the channel portion, and configured to store data by a resistance level set for each of the plurality of cell portions.

A memory device includes a transistor and a memory cell. The transistor includes a first gate electrode, a second gate electrode, a channel layer, and a gate dielectric layer. The second gate electrode is over the first gate electrode. The channel layer is located between the first gate electrode and the second gate electrode. The gate dielectric layer is located between the channel layer and the second gate electrode. The memory cell is sandwiched between the first gate electrode and the channel layer.

A memory device includes a plurality of first memory cells disposed along a vertical direction. Each of the plurality of first memory cells includes a portion of a first channel segment that extends along the vertical direction and has a first sidewall and a second sidewall. The first and second sidewalls of the first channel segment facing toward and away from a first lateral direction, respectively. Each of the plurality of first memory cells includes a portion of a first ferroelectric segment that also extends along the vertical direction and is in contact with the first sidewall of the first channel segment. A width of the first ferroelectric segment along a second lateral direction is different from a width of the first channel segment along the second lateral direction. The second lateral direction is perpendicular to the first lateral direction.

A memory device includes a plurality of memory sub-arrays. Each of the memory sub-arrays is accessed through a staircase of word lines (WLs) and a plurality of interconnect structures. The memory device includes a plurality of test structures. Each of the test structures corresponds to one of the memory sub-arrays, and includes: (i) a staircase of test WLs that emulate the staircase of WLs coupled to the corresponding memory sub-array, and (ii) a plurality of test interconnect structures that emulate the interconnect structures coupled to the corresponding memory sub-array. The plurality of test structures are electrically coupled to one another in series.

According to an embodiment, a non-volatile memory device includes a first conductive layer, electrodes, an interconnection layer and at least one semiconductor layer. The electrodes are arranged between the first conductive layer and the interconnection layer in a first direction perpendicular to the first conductive layer. The interconnection layer includes a first interconnection and a second interconnection. The semiconductor layer extends through the electrodes in the first direction, and is electrically connected to the first conductive layer and the first interconnection. The device further includes a memory film between each of the electrodes and the semiconductor layer, and a conductive body extending in the first direction. The conductive body electrically connects the first conductive layer and the second interconnection, and includes a first portion and a second portion connected to the second interconnection. The second portion has a width wider than the first portion.

A method for forming a semiconductor memory structure includes following operations. A plurality of doped regions are formed in a semiconductor substrate. The doped regions are separated from each other. A stack including a plurality of first insulating layers and a plurality of second insulating layers alternately arranged is formed over the semiconductor substrate. A first trench is formed in the stack. The second insulating layers are replaced with a plurality of conductive layers. A second trench is formed. A charge-trapping layer and a channel layer are formed in the second trench. An isolation structure is formed to fill the second trench. A source structure and a drain structure are formed at two sides of the isolation structure.

A semiconductor memory device includes: a first semiconductor layer extending in a first direction; a first conductive layer and a second conductive layer that are arranged in the first direction and each opposed to the first semiconductor layer; a first insulating portion disposed between the first semiconductor layer and the first conductive layer, the first insulating portion containing oxygen (O) and hafnium (Hf); a second insulating portion disposed between the first semiconductor layer and the second conductive layer, the second insulating portion containing oxygen (O) and hafnium (Hf); and a first charge storage layer disposed between the first insulating portion and the second insulating portion, the first charge storage layer being spaced from the first conductive layer and the second conductive layer.

A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line, the common source line and the common bit line formed on a first side of the channel region and the ferroelectric gate dielectric layer and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes formed on a second side, opposite the first side, of the ferroelectric gate dielectric layer.

A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line that are formed on a first side of the channel region, away from the ferroelectric gate dielectric layer, and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes that are formed adjacent the ferroelectric gate dielectric layer on a second side, opposite the first side, of the channel region.