A ferroelectric memory device includes interlayer insulating layers and gate lines alternately stacked, a data storage layer vertically passing through the interlayer insulating layers and the gate lines and having a cylindrical shape, and a channel layer formed in an area enclosed by the data storage layer. The data storage layer includes a first ferroelectric layer abutting on the channel layer, a second ferroelectric layer abutting on the interlayer insulating layers and the gate lines, and an interface layer formed between the first and the second ferroelectric layers.

The disclosed technology generally relates to memory structures, for example for a vertical NAND memory. In one aspect, a memory structure includes a substrate and a layer stack arranged on a surface of the substrate, wherein the layer stack includes one or more conductive material layers alternating with one or more dielectric material layers. The memory structure can also include a trench in the layer stack, wherein the trench is formed through the one or more conductive material layers, and wherein the trench includes inner side walls. The memory structure also includes a programmable material layer arranged in the trench and which covers the inner side walls of the trench. The memory structure further includes an oxide semiconductor layer arranged in the trench over the programmable material layer.

Semiconductor devices and methods of manufacture are provided wherein a ferroelectric random access memory array is formed with bit line drivers and source line drivers formed below the ferroelectric random access memory array. A through via is formed using the same processes as the processes used to form individual memory cells within the ferroelectric random access memory array.

Provided is a memory cell including a channel material contacting a source line and a bit line; a ferroelectric (FE) material contacting the channel material; and a word line contacting the FE material. The FE material is disposed between the channel material and the word line. The word line includes a bulk layer. The bulk layer includes a first metal layer; and a second metal layer. The second metal layer is sandwiched between the first metal layer and the FE material.

A memory array includes a first bit-line stack disposed over a substrate, a first spacer, a first data storage structure, and a word line. The first bit-line stack includes a first bit line disposed over the substrate; and a first hard mask layer partially covering a top surface of the first bit line. The first spacer is disposed on a lower sidewall of a first sidewall of the first bit line. The first hard mask layer and the first spacer expose a top corner of the first bit line. The first data storage structure covers the top corner of the first bit line. The word line covers a sidewall of the first data storage structure.

A memory cell includes a thin film transistor over a semiconductor substrate. The thin film transistor includes a memory film contacting a word line, an oxide semiconductor (OS) layer contacting a source line and a bit line, and a conductive feature interposed between the memory film and the OS layer. The memory film is disposed between the OS layer and the word line. A dielectric material covers sidewalls of the source line, the memory film, and the OS layer.

A performance of a memory cell including a ferroelectric film is improved. Reliability of the memory cell is ensured. A semiconductor device having a memory cell includes: a plurality of semiconductor layers configuring a channel region; a pair of semiconductor layers SI2 provided so as to sandwich the plurality of semiconductor layers SI1 in an X direction, connected to the plurality of semiconductor layers SI1, and configuring a source region and a drain region; a plurality of paraelectric films IL covering outer peripheries of the plurality of semiconductor layers SI1, respectively; a bottom electrode BE covering outer peripheries of the plurality of paraelectric films IL between the pair of semiconductor layers SI2; a ferroelectric film FE formed on the bottom electrode BE; and a top electrode TE formed on the ferroelectric film FE.

Memory devices and a method of fabricating memory devices are disclosed. In one aspect, the method includes forming a plurality of first transistors in a first area and a plurality of second transistors in a second area and forming a stack over the second area. The method includes forming a memory array portion and an interface portion through the stack. The memory array portion includes memory strings and the interface portion includes first conductive structures extending along a lateral direction. The method further includes simultaneously forming second conductive structures in the first area and forming third conductive structures in the second area. The second conductive structures each vertically extend to electrically couple to at least one of the first transistors, and the third conductive structures each vertically extend through one of the memory strings to electrically couple to at least one of the second transistors.

A non-volatile memory device is provided. The nonvolatile memory device includes a metal pillar, a channel layer separated from the metal pillar and surrounding a side surface of the metal pillar, a source arranged on one end of the channel layer, a drain arranged on the other end of the channel layer, a gate insulating layer surrounding a side surface of the channel layer, and a plurality of insulating elements and a plurality of gate electrodes alternately arranged along a surface of the gate insulating layer and surrounding a side surface of the gate insulating layer.

A 3-dimensional vertical memory string array includes high-speed ferroelectric field-effect transistor (FET) cells that are low- cost, low-power, or high-density and suitable for SCM applications. The memory circuits of the present invention provide random-access capabilities. The memory string may be formed above a planar surface of substrate and include a vertical gate electrode extending lengthwise along a vertical direction relative to the planar surface and may include (i) a ferroelectric layer over the gate electrode, (ii) a gate oxide layer; (iii) a channel layer provided over the gate oxide layer; and (iv) conductive semiconductor regions embedded in and isolated from each other by an oxide layer, wherein the gate electrode, the ferroelectric layer, the gate oxide layer, the channel layer and each adjacent pair of semiconductor regions from a storage transistor of the memory string, and wherein the adjacent pair of semiconductor regions serve as source and drain regions of the storage transistor.