A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.

A semiconductor device includes a stacked structure including conductive layers and gaps respectively interposed between the conductive layers, a channel layer passing through the stacked structure, a ferroelectric layer surrounding a sidewall of the channel layer, and first dielectric patterns interposed between the ferroelectric layer and the conductive layers, respectively. The gaps extending between the first dielectric patterns.

Some embodiments include an integrated assembly having a ferroelectric transistor body region between a first comparative digit line and a second comparative digit line. A carrier-reservoir structure is coupled with the ferroelectric transistor body region through an extension that passes along a side of the first comparative digit line. Some embodiments include an integrated assembly having a conductive structure over a carrier-reservoir structure. A bottom of the conductive structure is spaced from the carrier-reservoir structure by an insulative region. A ferroelectric transistor is over the conductive structure. The ferroelectric transistor has a bottom source/drain region over the conductive structure, has a body region over the bottom source/drain region, and has a top source/drain region over the body region. An extension extends upwardly from the carrier-reservoir structure, along a side of the conductive structure, and to a bottom of the body region. Some embodiments include methods of forming integrated assemblies.

A semiconductor memory device that may include a substrate, an array of memory cells arranged in rows and columns, bit lines and word lines. The memory cells each may include a pillar-shaped active region extending vertically, which includes source/drain regions at upper and lower ends respectively and a channel region between the source/drain regions. The channel region may include a single-crystalline semiconductor material. The memory cells each may further include a gate stack formed around a periphery of the channel region. Each of the bit lines is located below a corresponding column, and electrically connected to the lower source/drain regions of the respective memory cells in the corresponding column. Each of the word lines is electrically connected to the gate stacks of the respective memory cells in a corresponding row.

Various embodiments of the present disclosure are directed towards a metal-ferroelectric-insulator-semiconductor (MFIS) memory device, as well as a method for forming the MFIS memory device. According to some embodiments of the MFIS memory device, a lower source/drain region and an upper source/drain region are vertically stacked. A semiconductor channel overlies the lower source/drain region and underlies the upper source/drain region. The semiconductor channel extends from the lower source/drain region to the upper source/drain region. A control gate electrode extends along a sidewall of the semiconductor channel and further along individual sidewalls of the lower and upper source/drain regions. A gate dielectric layer and a ferroelectric layer separate the control gate electrode from the semiconductor channel and the lower and upper source/drain regions.

According to one embodiment, a semiconductor memory device includes a ferroelectric layer and a first semiconductor layer. The first semiconductor layer is electrically connected to a first electrode and a second electrode and includes an n-type oxide semiconductor. A third electrode is opposite the first semiconductor layer. The ferroelectric layer is between the third electrode and the first semiconductor layer. A second semiconductor layer includes at least one of a Group IV semiconductor material or a p-type oxide semiconductor material. The first semiconductor layer is between the ferroelectric layer and the second semiconductor layer.

Memory devices are implemented within a vertical memory structure, comprising a stack of alternating layers of insulator material and word line material, with a series of alternating conductive pillars and insulating pillars disposed through stack. Data storage structures are disposed on inside surfaces of the layers of word line material at cross-points of the insulating pillars and the layers of word line material. Semiconductor channel material is disposed between the insulating pillars and the data storage structures at cross-points of the insulating pillars with the layers of word line material. The semiconductor channel material extends around an outside surface of the insulating pillars, contacting the adjacent conductive pillars on both sides to provide source/drain terminals.

A semiconductor die comprises a device portion comprising: an array of active memory devices extending in a first direction, and interface portions located adjacent to axial ends of the device portion in the first direction. The interface portions have a staircase profile in a vertical direction and comprise an array of dummy memory devices and an array of gate vias. The dummy memory devices are axially aligned with the active memory devices in the first direction, each dummy memory device comprising at least one interface via. Moreover, each row of the array of gate vias extends in the first direction and is located parallel to a row of the array of dummy memory devices in a second direction perpendicular to the first direction. Each gate via is electrically coupled to the at least one interface via of a dummy memory device located adjacent thereto.

In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

A memory device includes a semiconductor channel, a gate electrode, and a stack located between the semiconductor channel and the gate electrode. The stack includes, from one side to another, a first ferroelectric material portion, a second ferroelectric material portion, and a gate dielectric portion that contacts the semiconductor channel.