Ferroelectric devices, including FeFET and/or FeRAM devices, include ferroelectric material layers deposited using atomic layer deposition (ALD). By controlling parameters of the ALD deposition sequence, the crystal structure and ferroelectric properties of the ferroelectric layer may be engineered. An ALD deposition sequence including relatively shorter precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having relatively uniform crystal grain sizes and a small mean grain size (e.g., ≤3 nm), which may provide effective ferroelectric performance. An ALD deposition sequence including relatively longer precursor pulse durations and purge durations between successive precursor pulses may provide a ferroelectric layer having less uniform crystal grain sizes and a larger mean grain size (e.g., ≥7 nm). Ferroelectric layers having larger mean grain sizes may exhibit enhanced crystallinity and a stabilized orthorhombic crystal phase, particularly in relatively thin layers (e.g., ≤15 nm in thickness).

A semiconductor device structure includes a silicon-on-insulator (SOI) region. The SOI region includes a semiconductor substrate, a buried oxide layer disposed over the semiconductor substrate, and a silicon layer disposed over the buried oxide layer. The semiconductor device structure also includes a first shallow trench isolation (STI) structure penetrating through the silicon layer and the buried oxide layer and extending into the semiconductor substrate. The first STI structure includes a first liner contacting the semiconductor substrate and the silicon layer, a second liner covering the first liner and contacting the buried oxide layer, and a third liner covering the second liner. The first liner, the second liner and the third liner are made of different materials. The first STI structure also includes a first trench filling layer disposed over the third liner and separated from the second liner by the third liner.

A memory device according to an embodiment includes a semiconductor layer, a gate electrode layer, and a first dielectric layer provided between the semiconductor layer and the gate electrode layer. The first dielectric layer contains aluminum (Al), a first element, nitrogen (N), and silicon (Si). The first element is at least one element selected from the group consisting of scandium (Sc), yttrium (Y), lanthanoid (Ln), boron (B), gallium (Ga), and indium (In).

[Object] To provide a semiconductor element capable of realizing an element having a nonvolatile memory capable of stably storing highly integrated data, a nonvolatile memory device, a multiply-accumulate operation device, and a method of manufacturing the semiconductor element. [Solving means] A semiconductor element according to an embodiment of the present technology includes a plurality of cell blocks. The plurality of cell blocks are configured by connecting a plurality of cell portions in series with each other, the plurality of cell portions each having a MOSFET for controlling conduction of a channel portion and a resistor connected in parallel to the channel portion, and configured to store data by a resistance level set for each of the plurality of cell portions.

A memory device includes a transistor and a memory cell. The transistor includes a first gate electrode, a second gate electrode, a channel layer, and a gate dielectric layer. The second gate electrode is over the first gate electrode. The channel layer is located between the first gate electrode and the second gate electrode. The gate dielectric layer is located between the channel layer and the second gate electrode. The memory cell is sandwiched between the first gate electrode and the channel layer.

A memory device includes a plurality of first memory cells disposed along a vertical direction. Each of the plurality of first memory cells includes a portion of a first channel segment that extends along the vertical direction and has a first sidewall and a second sidewall. The first and second sidewalls of the first channel segment facing toward and away from a first lateral direction, respectively. Each of the plurality of first memory cells includes a portion of a first ferroelectric segment that also extends along the vertical direction and is in contact with the first sidewall of the first channel segment. A width of the first ferroelectric segment along a second lateral direction is different from a width of the first channel segment along the second lateral direction. The second lateral direction is perpendicular to the first lateral direction.

A ferroelectric field effect transistor (FeFET) having a double-gate structure includes a first gate electrode, a first ferroelectric material layer over the first gate electrode, a semiconductor channel layer over the first ferroelectric material layer, source and drain electrodes contacting the semiconductor channel layer, a second ferroelectric material layer over the semiconductor channel layer, and a second gate electrode over the second ferroelectric material layer.

Memory cells include various versions of a capacitor structure including a polarization retention member. Each polarization retention member includes an antiferroelectric layer over a ferroelectric layer. The antiferroelectric layer, among other layers, can be tailored to customize the hysteresis loop shape, and the coercive electric field required to change polarization of the memory cell. Metal electrodes, and/or dielectric or metallic interlayers may also be employed to tailor the hysteresis. The memory cells can include FeRAMs or FeFETs. The memory cells provide a lower coercive electric field requirement compared to conventional ferroelectric memory cells, enhanced reliability, and require minimum changes to integrate into current integrated circuit fabrication processes.

A memory circuit includes a memory array including a plurality of memory cells, each memory cell of the plurality of memory cells including an n-type channel layer including a metal oxide material, and a gate structure overlying and adjacent to the n-type channel layer, the gate structure including a conductive layer overlying a ferroelectric layer. The memory circuit is configured to apply a gate voltage to each memory cell of the plurality of memory cells in first and second write operations, the gate voltage has a positive polarity and a first magnitude in the first write operation and a negative polarity and a second magnitude greater than the first magnitude in the second write operation.

An illustrative device disclosed herein includes at least one layer of insulating material, a conductive contact structure having a conductive line portion and a conductive via portion and a memory cell positioned in a first opening in the at least one layer of insulating material. In this illustrative example, the memory cell includes a bottom electrode, a memory state material positioned above the bottom electrode and an internal sidewall spacer positioned within the first opening and above at least a portion of the memory state material, wherein the internal sidewall spacer defines a spacer opening and wherein the conductive via portion is positioned within the spacer opening and above a portion of the memory state material.